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UART_FINAL
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UART_FINAL
vimalmahanthy
over 4 years ago
#include "LPC17xx.h" // Device header
enum state_t{idle=0,AA,Cal_lnth,Evt_Data_clt,Cmd_Data_clt,Ack_Data_clt,cal_Check_sum};
enum events_t{aa=0x55,event=0x55,BB=0xbb,ack=0x33,cmd=0xcc,length};
uint16_t time_out=0;
uint8_t packet[32],Index=0,Event,ps,Start,Flag,sum=0,loop_counter,process=0,*ptr,Packet_size=0,timeout=0;
uint8_t Evt_ack_to_tx[] = {"Event PACKET IS VALID"};
uint8_t CMD_ack_to_tx[] = {"COMMAND PACKET IS VALID"};
uint8_t ACK_ack_to_tx[] = {"ACKNOWLEDGE PACKET IS VALID"};
uint8_t Evt1_ack_to_tx[] = {"Event PACKET IS INVALID"};
uint8_t CMD1_ack_to_tx[] = {"COMMAND PACKET IS INVALID"};
uint8_t ACK1_ack_to_tx[] = {"ACKNOWLEDGE IS INVALID"};
/*struct State_Matrix
{
enum state_t Current_state;
enum events_t Current_event;
enum state_t Next_state;
}
S_Matrix[] = { { idle , aa, AA },
{ AA , event, Evt_Data_clt },
{ AA , cmd, Cmd_Data_clt },
{ AA , ack, Ack_Data_clt },
{Evt_Data_clt , length, cal_Check_sum },
{Ack_Data_clt , length, cal_Check_sum },
{Cmd_Data_clt , length, cal_Check_sum },
{ AA , timeout, idle },
{Cal_lnth , timeout, idle },
{Evt_Data_clt , timeout, idle },
{Ack_Data_clt , timeout, idle },
{Cmd_Data_clt , timeout, idle },
};
void f1(uint8_t i,uint8_t a[]);
void f2(uint8_t i,uint8_t *ptr);
void f3();
enum events_t f4();
enum events_t f5();
enum events_t f6();
struct State_function
{
char name[20];
void (*func)();
};
Function[] = { {" idle ", &f1 },
{" AA ", &f2 },
{"Cal_lnth ", &f3 },
{"Evt_Data_clt ", &f4 },
{"Cmd_Data_clt ", &f5 },
{"Ack_Data_clt ", &f6 },
};
void f1(uint8_t i,uint8_t a[])
{
while(packet[i]!=aa)
i++;
ps = AA;
}
void f2(uint8_t i,uint8_t *ptr)
{
LPC_TIM0->TCR = 1;
if(packet[i] == 0x55)
*ptr = Evt_Data_clt;
else if(packet[i] == 0x33)
*ptr = Ack_Data_clt;
else if(packet[i] == 0x55)
*ptr = Cmd_Data_clt;
else
;
}
void f3()
{
LPC_TIM0->TCR = 1;
}
enum events_t f4()
{
LPC_TIM0->TCR = 1;
if(length>16)
ps = cal_Check_sum;
}
enum events_t f5()
{
LPC_TIM0->TCR = 1;
if(length>14)
ps = cal_Check_sum;
}
enum events_t f6()
{
LPC_TIM0->TCR = 1;
if(length>16)
ps = cal_Check_sum;
}
*/
void display(uint8_t var[])
{
uint8_t i = 0;
while(var[i++]!='\0')
{
while(LPC_UART0->LSR&(1<<5))
LPC_UART0->THR = var[i];
}
}
void Check_sum_validation()
{
uint8_t Length;
Length = sum;
process = 1;
loop_counter = 0;
if(packet[1]==0x55)
{
if(packet[15]==0xbb)
{
while(loop_counter<14)
sum += packet[loop_counter++];
if(sum==packet[14])
display(Evt_ack_to_tx);
else
display(Evt1_ack_to_tx);
}
}
else if(packet[1]==0x33)
{
while(loop_counter<12)
sum += packet[loop_counter++];
if(sum==packet[13])
display(ACK_ack_to_tx);
else
display(ACK1_ack_to_tx);
}
else
{
while(loop_counter<Length)
sum += packet[loop_counter++];
if(sum==(packet[Length]+packet[Length-1]))
display(CMD_ack_to_tx);
else
display(CMD1_ack_to_tx);
}
if(Flag!=1)
ps = idle;
process=0;
}
void data_collect()
{
uint8_t Length = sum;
LPC_TIM0->TCR = 1;
if(*ptr == 0x55)
{
while(Length++<13)
{
while(LPC_TIM0->IR==0)
;
LPC_TIM0->IR = 1;
if(~Flag)
{
ps = idle;
break;
}
else
Flag = 0;
LPC_TIM0->TCR=1;
}
}
else if(*ptr == 0x33)
{
while(Length++<13)
{
while(LPC_TIM0->IR==0)
;
LPC_TIM0->IR = 1;
if(~Flag)
{
ps = idle;
break;
}
else
Flag = 0;
LPC_TIM0->TCR=1;
}
}
else
{
while(Length++<Packet_size)
{
while(~timeout)
;
if(~Flag)
{
ps = idle;
break;
}
else
Flag = 0;
LPC_TIM0->TCR=1;
}
}
}
void Cmd_pck_size_clt()
{
uint8_t Length = 0;
LPC_TIM0->TCR=1;
while(Length<2&ps!=idle)
if(Flag)
{
sum += packet[(Length++)+2];
Flag = 0;
}
if(ps!=idle)
ps = Cmd_Data_clt;
}
int UART0_IRQHandler()
{
LPC_TIM0->TCR = 2;
packet[Index++] = LPC_UART0->RBR;
Flag = 1;
}
void TIMER0_IRQHandler()
{
LPC_TIM0->TCR = 2;//TIMER0_IRQHandler,precounter are reset
Index = 0;
ps = idle;
LPC_TIM0->IR = 1;//TIMER0 interrupt disabled
}
int main()
{
LPC_GPIO3->FIODIR3 = 0xff;
LPC_GPIO3->FIOPIN3 = 0x00;
LPC_SC->PCONP = (1<<3|3<<1);//poweron uart0 in pconp register at bit3 and timer0
LPC_SC->PCLKSEL0 = 0<<6;//peripheral clock select for uart0 in pclksel0 registers 6-7 bits
LPC_UART0->LCR = 1<<7;//divisor latch enabled in lcr register
LPC_UART0->DLL = 0xa1;//register contains lsb of divisor
LPC_UART0->DLM = 0x00;//register contains msb of divisor
LPC_UART0->FCR = 1;//enable fifo in fcr
LPC_PINCON->PINSEL0 = (1<<4)|(1<<6);//ENABLED UART0 TX & RX OF GPIO
LPC_UART0->LCR = 0<<7;//dlab=0
LPC_UART0->LCR = 3|(0<<2)|(0<<3);
LPC_GPIO3->FIODIR3 = 0xff;
LPC_GPIO3->FIOPIN3 = 0x00;
LPC_UART0->IER = 1;
NVIC->ISER[0] = (1<<5)|(1<<1);
LPC_SC->PCLKSEL0 = 0<<2;//peripherical=cclk is selected for timer0
LPC_TIM0->PR = 0;//precount register set to zero
LPC_TIM0->MR0 = 0xa2c3;
LPC_TIM0->MCR = 3;
NVIC_SetPriority(UART0_IRQn, 0);
while(1)
{
switch(ps)
{
case idle:
{
if(packet[0]==0xaa)
ps = AA;
else
Index = 0;
break;
}
case AA:
{
LPC_TIM0->TCR = 1;
if(packet[1]==0x55)
ps = Evt_Data_clt;
else if(packet[1]==0x33)
ps = Ack_Data_clt;
else if(packet[1]==0xcc)
ps = Cal_lnth;
else
;
break;
}
case Cal_lnth:
{
Cmd_pck_size_clt();
break;
}
case Evt_Data_clt:
{
data_collect();
break;
}
case Ack_Data_clt:
{
data_collect();
break;
}
case Cmd_Data_clt:
{
data_collect();
break;
}
case cal_Check_sum:
{
Check_sum_validation();
break;
}
}
}
}