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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>IENABLE and IDISABLE giving errorin RVCT</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/43334/ienable-and-idisable-giving-errorin-rvct</link><description> 
Dear all, I am using LPC 2132 controller. In nested interrupt
IENABLE and IDISABLE macros giving error in RVCT. 
The error is as below 

 
source\cpu.c(61): error: #20: identifier &amp;quot;LR&amp;quot; is undefined
source\cpu.c(61): error: #20: identifier &amp;quot;SP&amp;quot; is undefined</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: IENABLE and IDISABLE giving errorin RVCT</title><link>https://community.arm.com/thread/132976?ContentTypeID=1</link><pubDate>Sat, 28 Oct 2006 06:29:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2ba674ef-aef2-453b-83ba-94f140d0671e</guid><dc:creator>Keil Software Support Intl.</dc:creator><description>&lt;p&gt;&lt;p&gt;
See: &lt;a href="http://www.keil.com/support/docs/3229.htm"&gt;http://www.keil.com/support/docs/3229.htm&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: IENABLE and IDISABLE giving errorin RVCT</title><link>https://community.arm.com/thread/132798?ContentTypeID=1</link><pubDate>Sat, 30 Sep 2006 15:49:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:432b0acd-2446-4ce2-a18e-45b20fea91c7</guid><dc:creator>Viktor Bucher</dc:creator><description>&lt;p&gt;&lt;p&gt;
You have to write it in an assembly module&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: IENABLE and IDISABLE giving errorin RVCT</title><link>https://community.arm.com/thread/132573?ContentTypeID=1</link><pubDate>Sat, 30 Sep 2006 09:41:39 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:37b48d4c-3e8e-4216-b11b-0215632afe7d</guid><dc:creator>kannan K</dc:creator><description>&lt;p&gt;&lt;p&gt;
Then how can i use nested interrupt in RVCT.&lt;br /&gt;
S Rajan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: IENABLE and IDISABLE giving errorin RVCT</title><link>https://community.arm.com/thread/132267?ContentTypeID=1</link><pubDate>Sat, 30 Sep 2006 06:33:14 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ddd7f226-3431-452b-80da-6c6f399061d2</guid><dc:creator>Viktor Bucher</dc:creator><description>&lt;p&gt;&lt;p&gt;
You can&amp;#39;t use those macros in RVCT.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>