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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Difficulty debugging ISR issue.</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/43258/difficulty-debugging-isr-issue</link><description> 
I am using the MCBSTM32 evaluation board. I started with the
&amp;quot;blinky&amp;quot; project. 

 
I wanted to change it so that I could DMA a block of data from the
ADC to memory. OK, I did that and it worked fine. 

 
Next, I wanted to get an interrupt when the specified</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Difficulty debugging ISR issue.</title><link>https://community.arm.com/thread/76605?ContentTypeID=1</link><pubDate>Thu, 09 Oct 2008 09:29:35 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:826a3c45-9be0-4cf3-8b86-88332a349386</guid><dc:creator>Mark Deneen</dc:creator><description>&lt;p&gt;&lt;p&gt;
Thanks Leon and Robert, this was my problem.&lt;/p&gt;

&lt;p&gt;
I guess I should not trust the sample interrupt vector code. It
specifies &amp;quot;void DMA1_Channel1_IRQHandler(void)&amp;quot;, which as Leon noted
does not match the startup code. My IRQ functions properly now.&lt;/p&gt;

&lt;p&gt;
Thanks!&lt;/p&gt;

&lt;p&gt;
Mark&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Difficulty debugging ISR issue.</title><link>https://community.arm.com/thread/52263?ContentTypeID=1</link><pubDate>Thu, 09 Oct 2008 09:26:03 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f6fd6391-73f5-45bb-a708-e8cbfbd11e8a</guid><dc:creator>Robet McNamara</dc:creator><description>&lt;p&gt;&lt;p&gt;
Have you defined a Function and placed it in the Vector for
DMAChannel1_IRQHandler? (By default, just having a function with this
name and exporting it is enough to have it defined.)&lt;/p&gt;

&lt;p&gt;
It looks as if it is going to the default (which is just an
infinite branch).&lt;/p&gt;

&lt;p&gt;
If you do have a routine call DMACHannel1_IRQHandler then knowing
which interrupt is going there could be helpful too (Is it the
ADC_IRQHandler?)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Difficulty debugging ISR issue.</title><link>https://community.arm.com/thread/76604?ContentTypeID=1</link><pubDate>Thu, 09 Oct 2008 09:24:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:98211c20-f716-4288-b244-f77a5519e391</guid><dc:creator>Leon Montgolf</dc:creator><description>&lt;p&gt;&lt;p&gt;
Yes, actually I did so don&amp;#39;t give up!!&lt;/p&gt;

&lt;p&gt;
It ends up that in the stm32f10x_it.c and stm32f10x_it.h files I
used the names of the interrupts did not match those in STM32F10x.s!
(So much for consistency in programming). Anyway, I finally figured
out that this is the default point the program ends up at for an
unhandled interrupt.&lt;/p&gt;

&lt;p&gt;
Here is some code that might help you along. It is for the
MCBSTM32 and is just a snip of the initialization and interrupt
handler. It has been awhile since I touched this code, so I must
state that I can&amp;#39;t guarantee that it actually works anymore. It
should hopefully gets you going down the right path. Enjoy!&lt;/p&gt;

&lt;pre&gt;
#define DATA_BUFF_SIZE 128

typedef struct
{
        bool done;
        unsigned short data[DATA_BUFF_SIZE];
}DATA_BUFF;

#define DMA_INT_ENABLE 0x00000002

void DMAChannel1_IRQHandler(void)
{
        DMA_Channel1-&amp;gt;CCR   &amp;amp;=  ~DMA_INT_ENABLE;
    data_buff.done = TRUE;
        GPIOB-&amp;gt;ODR ^= (GPIOB-&amp;gt;ODR &amp;amp; 0xFFFF00FF) | 0x200;
}

void adc_Init (void)
{
//  GPIOA-&amp;gt;CRL &amp;amp;= ~0x0000000F;                    // set PIN1 as analog input (see stm32_Init.c)

  RCC-&amp;gt;AHBENR |= (1&amp;lt;&amp;lt;0);                          // enable periperal clock for DMA

        // Setup interrupt for DMA.
  DMA_Channel1-&amp;gt;CMAR  = (u32)data_buff.data; // set channel1 memory address
  DMA_Channel1-&amp;gt;CPAR  = (u32)&amp;amp;(ADC1-&amp;gt;DR);       // set channel1 peripheral address
  DMA_Channel1-&amp;gt;CNDTR = DATA_BUFF_SIZE;                      // transmit data buff size.
  DMA_Channel1-&amp;gt;CCR   = 0x000025A0;               // configure DMA channel
  DMA_Channel1-&amp;gt;CCR   |=  DMA_INT_ENABLE;

//  DMA_Channel1-&amp;gt;CCR   = 0x00002520;               // configure DMA channel

//  DMA_Channel1-&amp;gt;CCR   = 0x00002AA2;             // configure DMA channel:
                                                                                                //              Transfer Complete interrupt Enabled,
                                                                                                //              read from peripheral,
                                                                                                //              curcular mode (auto reload),
                                                                                                //              no peripheral increment,
                                                                                                //              memory increment,
                                                                                                //              32 bit perpherial and menory size,
                                                                                                //              high priority level
                                                                                                //              no memory to memory mode

  DMA_Channel1-&amp;gt;CCR  |= (1 &amp;lt;&amp;lt; 0);               // DMA Channel 1 enable

        // Enable interrupt
  NVIC-&amp;gt;Enable[0] |= (1 &amp;lt;&amp;lt; (DMAChannel1_IRQChannel &amp;amp; 0x1F)); // enable interrupt

  RCC-&amp;gt;APB2ENR |= (1&amp;lt;&amp;lt;9);                         // enable periperal clock for ADC1

  ADC1-&amp;gt;SQR1 &amp;amp;= ~0x00F00000;                      // only one conversion

  ADC1-&amp;gt;SMPR2 &amp;amp;= 0x00000038;                      // clear bits 3..5 (channel1)
  ADC1-&amp;gt;SMPR2 |= 0x00000028;                      // set sample time (55,5 cycles)

  ADC1-&amp;gt;SQR3  &amp;amp;= 0x0000001F;                      // clear bits 0..4
  ADC1-&amp;gt;SQR3  |= 0x00000001;                      // set rank

  ADC1-&amp;gt;CR1   =  0x00000100;                      // use independant mode, SCAN mode

  ADC1-&amp;gt;CR2   =  0x00000101;                      // use data align right, single conversion
                                                  // EXTSEL = Timer 1 CC1 event
                                                  // enable ADC, DMA mode, external Trigger
  ADC1-&amp;gt;CR2  |=  0x00500000;                                   // start conversion

}
&lt;/pre&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Difficulty debugging ISR issue.</title><link>https://community.arm.com/thread/52269?ContentTypeID=1</link><pubDate>Thu, 09 Oct 2008 08:45:55 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b1e3b871-547d-48f7-975d-666338544e9e</guid><dc:creator>Mark Deneen</dc:creator><description>&lt;p&gt;&lt;p&gt;
Leon,&lt;/p&gt;

&lt;p&gt;
Did you ever find a solution to this problem? I am having the
exact same issue. I&amp;#39;m about to give up on DMA and just use the ADC
alone.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>