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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>single stepping two instructions at a time, ISD51</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/42401/single-stepping-two-instructions-at-a-time-isd51</link><description> What would cause single step debugging through a module under the control of the ISD51 monitor to suddenly start stepping at 2 line intervals, and refusing to breakpoint at many locations? 
 
(The program suddenly takes on this behaviour, having started</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: single stepping two instructions at a time, ISD51</title><link>https://community.arm.com/thread/96478?ContentTypeID=1</link><pubDate>Thu, 22 Jul 2004 03:25:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:923dce41-7eb0-4b9f-9c0e-26df211018e5</guid><dc:creator>Jon Ward</dc:creator><description>&lt;p&gt;The cause of the effect you are seeing is that the 8051 blocks interrupts for more than a single instruction in some cases.  This happens when your program accesses an interrupt enable register or an interrupt priority register.  In such situations, ISD51 steps over two or more assembler instructions when single-stepping.&lt;br /&gt;
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There is no way around this.&lt;br /&gt;
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I just updated the ISD51 manual to include information about this effect.&lt;br /&gt;
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&lt;a href="http://www.keil.com/support/man/docs/isd51/isd51_sideeffects.htm"&gt;http://www.keil.com/support/man/docs/isd51/isd51_sideeffects.htm&lt;/a&gt;&lt;br /&gt;
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&lt;b&gt;Jon&lt;/b&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: single stepping two instructions at a time, ISD51</title><link>https://community.arm.com/thread/72625?ContentTypeID=1</link><pubDate>Wed, 21 Jul 2004 16:36:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:13a4c7b3-7b85-43a8-a454-3ed546527e6e</guid><dc:creator>Peter Williams</dc:creator><description>&lt;p&gt;It was assembler lines.&lt;br /&gt;
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If I was in mixed mode, it would be C lines. the underlying cause was presumably the monitor&amp;#39;s inability to rewriting the code while the higher priority irq was invoked. The monitor wrote the next instruction, apparently.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: single stepping two instructions at a time, ISD51</title><link>https://community.arm.com/thread/42526?ContentTypeID=1</link><pubDate>Wed, 21 Jul 2004 16:32:20 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:728c2f59-b10e-4bed-bc1f-8a6ba59e9cf7</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;Are you talking about assembler lines, or &amp;#39;C&amp;#39; source lines...?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: single stepping two instructions at a time, ISD51</title><link>https://community.arm.com/thread/42529?ContentTypeID=1</link><pubDate>Wed, 21 Jul 2004 15:33:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:85196622-e055-4cd1-920a-d67653c37d44</guid><dc:creator>Peter Williams</dc:creator><description>&lt;p&gt;well the answer is:&lt;br /&gt;
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if you have soft timers, where the tick timer is at a high priority than the ISD interrupt, the latter gets lost (regularly) - this manifests itself as single steps of more than 1 instruction.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>