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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>c51</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/42119/c51</link><description> I access the memory of w77e58 on-chip sram, 
whether it must be through Port P0 and P2 ,or 
not? </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: c51</title><link>https://community.arm.com/thread/40658?ContentTypeID=1</link><pubDate>Tue, 05 Aug 2003 11:35:47 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ab96f740-a5de-41df-99ab-d1e849e5cf67</guid><dc:creator>Oleg Sergeev</dc:creator><description>&lt;p&gt;Could you set and read docs little more?&lt;br /&gt;
Winbond has provided very informative data sheets. Read about DME0 bit of PMR (page 23) and Memory Organization (page 8).&lt;br /&gt;
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HINT: accessing internal memory has nothing with P0 and P2.&lt;br /&gt;
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Good days!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>