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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Imprecise bus access fault in Cortex M7</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/41118/imprecise-bus-access-fault-in-cortex-m7</link><description> 
I&amp;#39;m trying to write unit tests for non-executable SRAM. As a step
in that process, I try to execute code inside SRAM by putting some
Thumb opcodes in RAM and then executing them. The opcodes execute
fine if I put a tiny delay (~10 millisecs) before</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Imprecise bus access fault in Cortex M7</title><link>https://community.arm.com/thread/69397?ContentTypeID=1</link><pubDate>Fri, 23 Oct 2015 08:24:40 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:084b5a5f-e57c-4e29-93ae-7e16e71b077c</guid><dc:creator>edPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Might the processor need time to flush the data before you call
the code and starts to fill the pipeline? Self-modifying code must
take into account the pipeline and caching for lots of newer
architectures.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>