<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>LPC1778 interfacing with SRAM</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/40844/lpc1778-interfacing-with-sram</link><description> 
Hi, 

 
I am trying to initialize this model of SRAM (R1LV0816ASB –
5SI) to my LPC1778. I am currently tracing my code result through the
memtest code that I wrote but so far what I am seeing is let say in
address 0x98000000 onwards is just value FF</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: LPC1778 interfacing with SRAM</title><link>https://community.arm.com/thread/108057?ContentTypeID=1</link><pubDate>Tue, 13 Jan 2015 17:24:15 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a8c59a99-5860-4b80-ae3c-00c6083481f7</guid><dc:creator>Shyan Jenq Ho</dc:creator><description>&lt;p&gt;&lt;p&gt;
There pre tagged...&lt;/p&gt;

&lt;pre&gt;
static void pinConfig_SRAM(void) {
//Select slew rate and also config for EMC use = 0x201
LPC_IOCON-&amp;gt;P3_0 |= 0x201; /* D0 @ P3.0 */
LPC_IOCON-&amp;gt;P3_1 |= 0x201; /* D1 @ P3.1 */
LPC_IOCON-&amp;gt;P3_2 |= 0x201; /* D2 @ P3.2 */
LPC_IOCON-&amp;gt;P3_3 |= 0x201; /* D3 @ P3.3 */

LPC_IOCON-&amp;gt;P3_4 |= 0x201; /* D4 @ P3.4 */
LPC_IOCON-&amp;gt;P3_5 |= 0x201; /* D5 @ P3.5 */
LPC_IOCON-&amp;gt;P3_6 |= 0x201; /* D6 @ P3.6 */
LPC_IOCON-&amp;gt;P3_7 |= 0x201; /* D7 @ P3.7 */

LPC_IOCON-&amp;gt;P3_8 |= 0x201; /* D8 @ P3.8 */
LPC_IOCON-&amp;gt;P3_9 |= 0x201; /* D9 @ P3.9 */
LPC_IOCON-&amp;gt;P3_10 |= 0x201; /* D10 @ P3.10 */
LPC_IOCON-&amp;gt;P3_11 |= 0x201; /* D11 @ P3.11 */

LPC_IOCON-&amp;gt;P3_12 |= 0x201; /* D12 @ P3.12 */
LPC_IOCON-&amp;gt;P3_13 |= 0x201; /* D13 @ P3.13 */
LPC_IOCON-&amp;gt;P3_14 |= 0x201; /* D14 @ P3.14 */
LPC_IOCON-&amp;gt;P3_15 |= 0x201; /* D15 @ P3.15 */

LPC_IOCON-&amp;gt;P4_1 |= 0x201; /* A1 @ P4.1 */
LPC_IOCON-&amp;gt;P4_2 |= 0x201; /* A2 @ P4.2 */
LPC_IOCON-&amp;gt;P4_3 |= 0x201; /* A3 @ P4.3 */

LPC_IOCON-&amp;gt;P4_4 |= 0x201; /* A4 @ P4.4 */
LPC_IOCON-&amp;gt;P4_5 |= 0x201; /* A5 @ P4.5 */
LPC_IOCON-&amp;gt;P4_6 |= 0x201; /* A6 @ P4.6 */
LPC_IOCON-&amp;gt;P4_7 |= 0x201; /* A7 @ P4.7 */

LPC_IOCON-&amp;gt;P4_8 |= 0x201; /* A8 @ P4.8 */
LPC_IOCON-&amp;gt;P4_9 |= 0x201; /* A9 @ P4.9 */
LPC_IOCON-&amp;gt;P4_10 |= 0x201; /* A10 @ P4.10 */
LPC_IOCON-&amp;gt;P4_11 |= 0x201; /* A11 @ P4.11 */

LPC_IOCON-&amp;gt;P4_13 |= 0x201; /* A13 @ P4.13 */
LPC_IOCON-&amp;gt;P4_14 |= 0x201; /* A14 @ P4.14 */
LPC_IOCON-&amp;gt;P4_15 |= 0x201; /* A15 @ P4.15 */
LPC_IOCON-&amp;gt;P4_16 |= 0x201; /* A16 @ P4.16 */

LPC_IOCON-&amp;gt;P4_17 |= 0x201; /* A17 @ P4.17 */
LPC_IOCON-&amp;gt;P4_18 |= 0x201; /* A18 @ P4.18 */
LPC_IOCON-&amp;gt;P4_19 |= 0x201; /* A19 @ P4.19 */

LPC_IOCON-&amp;gt;P2_24 |= 0x201; /* /OE @ P2.24 ..EMC_CKE0*/
LPC_IOCON-&amp;gt;P4_25 |= 0x201; /* /WEN @ P4.25 */
LPC_IOCON-&amp;gt;P4_26 |= 0x201; /* /BLS0 @ P4.27 Lower Byte*/
LPC_IOCON-&amp;gt;P4_27 |= 0x201; /* /BLS1 @ P4.27 Upper Byte*/

LPC_IOCON-&amp;gt;P2_14 |= 0x201; /* /CS2 @ P2.14*/

}

void EMCInit (void)
{ //SRAM_INIT();
  pinConfig_SRAM();
  LPC_SC-&amp;gt;PCONP |= 0x00000800;

//LPC_SC-&amp;gt;EMCDLYCTL = 0x00001010;
//LPC_SC-&amp;gt;EMCDLYCTL |= (8&amp;lt;&amp;lt;0);
//LPC_SC-&amp;gt;EMCDLYCTL |= (8&amp;lt;&amp;lt;8);

//LPC_SC-&amp;gt;EMCDLYCTL |= (8&amp;lt;&amp;lt;16);
  LPC_SC-&amp;gt;EMCCLKSEL = 0x00000000; //CLCK = EMCCLK

  LPC_EMC-&amp;gt;Config = 0x00000000;
  LPC_EMC-&amp;gt;StaticExtendedWait = 0x00;
  /* Configure memory layout, but MUST DISABLE BUFFERs during configuration */
  /*The buffers can be enabled or disabled for static memory using the EMCStaticConfig     Registers.*/
  LPC_EMC-&amp;gt;StaticConfig2 = 0x00000081; //16bit &amp;amp; active low lower and upper byte select

  LPC_EMC-&amp;gt;StaticWaitWen2 = 0x00000001; //WaitWen0+1 Delay from CHip Select to Write Enable
  LPC_EMC-&amp;gt;StaticWaitWr2 = 0x00000001; // program the delay from the chip select to the write   access
  LPC_EMC-&amp;gt;StaticWaitOen2 = 0x00000001; // Chip Select to output enable or address change   whichever is later
  LPC_EMC-&amp;gt;StaticWaitRd2 = 0x00000001; //Chip select to read access
  //LPC_EMC-&amp;gt;StaticWaitPage2 = 0x00000000; //Delay for asynchronous page mode sequential accesses for EMC_CS0.
//LPC_EMC-&amp;gt;StaticWaitTurn2 = 0x00000000; //Number of bus turnaround cycles EMC_CS0.

  LPC_EMC-&amp;gt;Control = 0x00000001; //May not be needed
}

void Memtest(void)
{
  volatile unsigned long *start= (volatile unsigned long *) 0x98000000UL; //volatile unsigned          short *start= (volatile unsigned short *) 0x98000000;
int value=0; int i;
//for(i = 0; i &amp;lt; 1048576; i+= 4)
for(i = 0; i &amp;lt; 128; i+= 1) //try just 32 bytes first.
{
  *start = value;
  start++;
  value++; }
}

int main(void)
{
  EMCInit();
  while(1)
  {
   Memtest();
  }
}
&lt;/pre&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LPC1778 interfacing with SRAM</title><link>https://community.arm.com/thread/93312?ContentTypeID=1</link><pubDate>Tue, 13 Jan 2015 09:09:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:571ff275-823c-4550-8efd-d254bf64b162</guid><dc:creator>Westonsupermare Pier</dc:creator><description>&lt;p&gt;&lt;p&gt;
That&amp;#39;s why the instructions say to use PRE tags for source
code.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LPC1778 interfacing with SRAM</title><link>https://community.arm.com/thread/63415?ContentTypeID=1</link><pubDate>Tue, 13 Jan 2015 02:00:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5f535230-269c-4987-87d1-ea68924ec6d8</guid><dc:creator>Shyan Jenq Ho</dc:creator><description>&lt;p&gt;&lt;p&gt;
Ooppss the formatting is a bit off. The text indentation changed
after I posted the message. My apologies.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>