Hello everyone,
I am trying to make communication between an STM32F3 microcontroller and a custom board baser on PIC microcontroller using SPI protocol.
The STM32F3 acts as a Slave and the custom board as a Master. The clock is set to 10 MHz. I’m using NSS hardware, and getting EXTI once CS gets low in NSS pin. The CPOL and CPHA are compatible between the two boards. I am using Interrupt base communication in the Slave side. The application consists of: 1) The Master sends a command to the Slave, then a data of 4 bytes : This part works fine 2) The Master sends continuously different commands, The Slave process the command, then sends its proper data (4 bytes) depending on the received command. The Updating frequency sends by the Master is about 20 KHz.
I have a problem with the second case, in fact, when the Master sends a command, let’s say 0x01, the Slave process this address and then sends back a frame let’s say 0x410547AF.
In the MISO line the frame is shifted, c.a.d (0x47, 0xAF, 0x41, 0x05, 0x05) instead of (0xXX, 0x41,0x05, 0x47, 0xAF), because the first byte corresponds to the byte when the address is received. I also used the debug mode to view the SR register and I can see that the FIFO transmission level is always at 2, that explains why the frame is shifted by 2 bytes. But I can’t find a solution to my problem, do you have an idea what would be the problem please? If you want some code sample, I can post it. I hope that my problem is clear. Thanks in advance Best regards
Firmly suggest you to measure the waveform using a oscilloscope.
By this means you can clearly know the reason.
Thank you Jack,
With the oscilloscope,i can see that the frame is shifted.
The thing is i don't have the information about the frame at t0, because the master sending request continuously. So, the frame visualized using oscilloscope shows (0x47, 0xAF, 0x41, 0x05, 0x05)instead of (0x00, 0x41,0x05, 0x47, 0xAF),the frame send by the Slave is 0x410547AF.
The explanation that i find is at t0, the Slave is synchronized to the Master only with the two last bytes 0x41, 0x05 shifted by Two, the two first bytes, i imagine that are 0 . Then the 0x47, 0xAF still in the Tx FIFO(this explains the FIFO level is usually at 2 bytes). At t1, the Slave sends 0x47, 0xAF, then 0x41, 0x05 placed between time in the FIFO. This why in MISO line, i can see (0x47, 0xAF, 0x41, 0x05, 0x05)but i can't understand why 0x05 is redundant.
My problem could the latency when writing to Tx FIFO and to the DR register ?
Note: I measured the period of the Chip Select and is about 12µs
May be it's not sufficient to the Slave to respond quickly ?
If hope that u can have an idea or explanation to this issue,
Best Regards
Note that if the master performs one more byte transfer than the slave expects, then it's likely that the last byte the slave sent will be repeated because the slave hasn't any newer data available in the FIFO.
One thing here - SPI can run unsynchronized forever if you don't design a specific synchronization state. Activation of the slave select is intended to synchronize master and slave. If you keep that slave select infinitely active, then it's enough with a single spurious bit on the clock signal to make master and slave one bit off. And if the slave processor hasn't completely booted when the master starts to communicate, then the slave can constantly be one or more bytes - or individual bits - off.
So in the end - are you regularly toggling the slave select signal, and making sure that the slave ends up with zero incomming/outgoing bytes the next time the master activates the slave select and starts a new transfer?
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