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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>SBUF physically two registers? and shift register</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/40343/sbuf-physically-two-registers-and-shift-register</link><description> 
My first question is regarding SBUF register of 8051. How come it
is two registers while locations is only one i.e; 99H. we call SBUF
physically two registers (write only and read only two separate
distinct registers as scott mackenzie calls it in his</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: SBUF physically two registers? and shift register</title><link>https://community.arm.com/thread/120164?ContentTypeID=1</link><pubDate>Thu, 03 Oct 2013 05:22:02 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:43ca9bd7-fe16-48b5-9a3a-378002eefb46</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
For an UART, you don&amp;#39;t want to merge register with serial register
- you want to be able to start receiving a second character in the
shift register while the processor waits for the program to pick up
the received byte from a buffer.&lt;/p&gt;

&lt;p&gt;
And preferably, you want to be able to store a byte to send while
the send shift register is busy shifting out a byte - this allows the
processor to be able to shift out the stop bits and then decide to
start with start bit + next byte instead of having to wait for the
software to react and insert a new character to send.&lt;/p&gt;

&lt;p&gt;
But some simple SPI implementations do integrate everything.&lt;/p&gt;

&lt;p&gt;
But as noted - you don&amp;#39;t need to know what makes the individual
transistors switch their states. What you need to know is what
register flags to keep track off, what can trig an interrupt and what
reaction times you are allowed when on the receiving end and if you
as sender can enqueue many characters without having to wait for any
shift register ticking.&lt;/p&gt;

&lt;p&gt;
The documentation for the UART:s contains the relevant information
- the actual implementation is left for the silicon engineers.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SBUF physically two registers? and shift register</title><link>https://community.arm.com/thread/107314?ContentTypeID=1</link><pubDate>Thu, 03 Oct 2013 04:21:45 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:af201268-b72d-4f31-993b-cf1d8dc6ab0c</guid><dc:creator>Ash J</dc:creator><description>&lt;p&gt;&lt;p&gt;
It can be any thing at the hardware level. Why bother that much as
long as you have a brief understanding of the operation.&lt;/p&gt;

&lt;p&gt;
The read-only SBUF can be a SIPO register&lt;br /&gt;
&lt;b&gt;(serial in parallel out, with read signal acting as enable output
signal and Rxd pin connected to serial input and the parallel output
connected to data bus);&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
and write-only SBUF can be a PISO register&lt;br /&gt;
&lt;b&gt;(parallel in serial out, with write signal acting as enable input
signal and data bus connected to parallel input and the serial output
connected to Txd output pin)&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
and there is not separate shift-register at-all.&lt;/p&gt;

&lt;p&gt;
PS: for better understanding of the terms, you must know the four
basic register configurations, Viz, SIPO, SISO, PIPO, PISO.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SBUF physically two registers? and shift register</title><link>https://community.arm.com/thread/81480?ContentTypeID=1</link><pubDate>Thu, 03 Oct 2013 04:05:17 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8f885e83-b91b-4f06-a9b3-1d74d6573b26</guid><dc:creator>Modulated Symbol</dc:creator><description>&lt;p&gt;&lt;p&gt;
Thanks but does that mean that write only register and read only
register are actually SBUF while shift register is a different
entity? is shift register also some where in the SFR or is it in
general purpose RAM?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SBUF physically two registers? and shift register</title><link>https://community.arm.com/thread/68389?ContentTypeID=1</link><pubDate>Thu, 03 Oct 2013 03:55:06 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f9ca6b2c-0c91-40a0-a95a-9b295d78ee9d</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
If you have &amp;quot;one&amp;quot; register, then you would normally expect that
you can write a value to it, and then read back that value again - or
maybe with some undefined bits zeroed in the answer. Anyway - there
is the expectation that read and write somehow belong together.&lt;/p&gt;

&lt;p&gt;
Not so with the UART data register. A write to that address writes
to a write-only register that buffers data to be handed over to the
shift-register for serial transmission. A read to that address will
perform a read of a completely different register that gets its value
from the last byte received by that shift register.&lt;/p&gt;

&lt;p&gt;
And for some chips, there is additional FIFO buffers inserted
between the read and write registers and the shift register handling
the actual serial communication.&lt;/p&gt;

&lt;p&gt;
Allmost all microcontrollers have this concept with a read
register and a write register sharing the same address for
incomming/outgoing data to the different peripherials. So you can
find it for I2C, SPI, ...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>