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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Using a SPI RAM for heap</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/40149/using-a-spi-ram-for-heap</link><description> 
I&amp;#39;m using the MDK-ARM and I would like to use an external RAM IC
that communicates through SPI as my Stack/heap RAM. instead of the
internal RAM that is on my Micro. I just can&amp;#39;t seem to find a good
resource or tutorial on how to do this. I believe</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Using a SPI RAM for heap</title><link>https://community.arm.com/thread/128110?ContentTypeID=1</link><pubDate>Sat, 06 Apr 2013 22:29:58 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d99953fb-5398-48bb-b718-0bb19178d102</guid><dc:creator>Mike Kleshov</dc:creator><description>&lt;p&gt;&lt;p&gt;
That refers to off-chip memory that sits on a parallel bus and is
mapped to address space.&lt;br /&gt;
By the way, some processors can map SPI memory to address space. But
normally this is used for booting off SPI flash memory, and it will
be too slow for many purposes.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using a SPI RAM for heap</title><link>https://community.arm.com/thread/117250?ContentTypeID=1</link><pubDate>Sat, 06 Apr 2013 15:04:44 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:698a42ad-841c-413b-b239-89d0ade32c49</guid><dc:creator>jeff belz</dc:creator><description>&lt;p&gt;&lt;p&gt;
So, why does uVision have an option for &amp;quot;Off-chip&amp;quot; RAM for
read/write memory? RAM1, RAM2, and RAM3. under the &amp;quot;Options for
target&amp;quot; window. If I want to use utilize that, what do I need?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using a SPI RAM for heap</title><link>https://community.arm.com/thread/107006?ContentTypeID=1</link><pubDate>Sat, 06 Apr 2013 14:32:56 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5d9fc643-7fc7-462a-be83-32c551bcd557</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Yes - especially since we are talking about the stack.&lt;/p&gt;

&lt;p&gt;
It would be like a PC with almost zero memory, resulting in almost
all memory accesses trigging a swap.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using a SPI RAM for heap</title><link>https://community.arm.com/thread/92271?ContentTypeID=1</link><pubDate>Sat, 06 Apr 2013 11:54:25 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8714d2f5-54f9-4c1f-a0a0-e5cec1a0dad9</guid><dc:creator>Mike Kleshov</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;How would the processor know that it have to perform SPI
communication to access memory?&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
Well, you could use an address space region that causes a hard
fault when accessed. Then do the magic in the hard fault handler.
With some read-ahead and caching you could achieve performance that&amp;#39;s
better than abysmal. This would take considerable development effort,
however.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Using a SPI RAM for heap</title><link>https://community.arm.com/thread/68200?ContentTypeID=1</link><pubDate>Sat, 06 Apr 2013 11:16:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c82c45cc-ca9f-454d-8b8e-bffaab966fef</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
You believe this is a uVision question?&lt;/p&gt;

&lt;p&gt;
Turn it around. How would the processor know that it have to
perform SPI communication to access memory? The processor is used to
be able to store a 32-bit integer with a single write - how will it
manage that if that write has to be captured by a SPI device that
would need to tick through 32 individual bits (after first having
received the address which also would take a huge number of
bits)?&lt;/p&gt;

&lt;p&gt;
Serial interfaces are for implementing &amp;quot;disk-type&amp;quot; of memory
access. Like read/write of blocks of data. Intel played a bit with
serial memories (RAMBUS) because some Intel big-wigs made a deal
where they would get a percentage of the ownership of RAMBUS when
RAMBUS would magically become billions and billions of dollars. The
route? By Intel only supporting native access to serial RAM. The
outcome? Intel had to glue serial-to-parallel adapters on their
motherboards, while the rest of the world implemented motherboards
using competitors memory controller interfaces.&lt;/p&gt;

&lt;p&gt;
Serial RAM just doesn&amp;#39;t give quick direct access, but instead
requires lots of complicated buffering.&lt;/p&gt;

&lt;p&gt;
So in short: what you want, and what you can do, is not always the
same thing. Settle for serial memories for database-operating code
having functions like: read_record(), write_record(), ...&lt;/p&gt;

&lt;p&gt;
Anything that needs to be accessed using a pointer has to be in
parallel-accessed memory within the processors memory space. And that
includes the stack (think about that poor stack pointer trying to
specify a location in an external SPI-memory that uses a few memory
addresses inside the processor memory space to span potentially huge
amounts of memory) and the heap.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>