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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Not able to enter into ISR even after interrupt is generated in LPC2294</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/40094/not-able-to-enter-into-isr-even-after-interrupt-is-generated-in-lpc2294</link><description> 
Dear Sir, 

 
The following code is working fine in simulator mode, when TC is
matching with MR0 interrupt is getting generated and the control is
moving to timer1 ISR. 

 
If the same code if it is loaded to the hardware board the code is
running fine</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Not able to enter into ISR even after interrupt is generated in LPC2294</title><link>https://community.arm.com/thread/61713?ContentTypeID=1</link><pubDate>Sun, 03 Mar 2013 22:21:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:24b520b4-317e-49a0-906f-e0645dd4ff1f</guid><dc:creator>siva k</dc:creator><description>&lt;p&gt;&lt;p&gt;
hi all,&lt;/p&gt;

&lt;p&gt;
I got the solution now the timer is working fine with my
hardware.&lt;/p&gt;

&lt;p&gt;
I have defined the default ISR and its address is stored in
VICDefVectAddr.&lt;/p&gt;

&lt;p&gt;
Thanks to all,&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Not able to enter into ISR even after interrupt is generated in LPC2294</title><link>https://community.arm.com/thread/61718?ContentTypeID=1</link><pubDate>Wed, 27 Feb 2013 00:50:07 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d6336abb-db2f-417b-8e80-349422f9bf4c</guid><dc:creator>BaEjack Zhang</dc:creator><description>&lt;p&gt;&lt;p&gt;
Check your startup file to see if your interrupt service routines
were correctly loaded, i.e. your interrupt vector table.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>