AT89C51 ADC in Timer Interrupt Problem

Hi there,

This may be a compiler/driver issue or it may be a hardware issue but I am wondering if anyone else has seen a similar problem to this.

We have code to read an ADC channel and this works fine. We have code to generate timer interrupts and handle CAN communications and this works fine.

However, when we call the ADC channel read from inside a timer interrupt (timer1, specially used just for this) it appears to completely screw up the CAN transmission. We get transmission on odd channels, bad data, all sorts.

Before I post lots of code as each system is quite complex, has anyone ever heard of this or a similar problem ? I have checked all the 89C51 errata sheets and gone through the assembly code produced by the Kiel and nowhere does there seem to be any connection between the two. Even with the ADC read in the interrupt it only occupies 2% of the processor time so I don't think it's to do with load or latency. I have made sure the ADC interrupt is off so it doesn't create an interrupt within an interrupt.

Thanks for any help,

Dirk

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  • However, when we call the ADC channel read from inside a timer interrupt (timer1, specially used just for this) it appears to completely screw up the CAN transmission. We get transmission on odd channels, bad data, all sorts.

    I can only guess, but here's a few potential problems I would check for:

    1. Register bank issues. Do the ISR and the function to read the the ADC channel use the same memory bank? If there's a problem here, the call could corrupt registers for other parts of the program.

    2. ISR priority issues. What other ISRs are there, and what priorities do they have?

    Even with the ADC read in the interrupt it only occupies 2% of the processor time so I don't think it's to do with load or latency. <p>

    3. Maybe it occupies those 2% at times when it shouldn't be occupying them.

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  • However, when we call the ADC channel read from inside a timer interrupt (timer1, specially used just for this) it appears to completely screw up the CAN transmission. We get transmission on odd channels, bad data, all sorts.

    I can only guess, but here's a few potential problems I would check for:

    1. Register bank issues. Do the ISR and the function to read the the ADC channel use the same memory bank? If there's a problem here, the call could corrupt registers for other parts of the program.

    2. ISR priority issues. What other ISRs are there, and what priorities do they have?

    Even with the ADC read in the interrupt it only occupies 2% of the processor time so I don't think it's to do with load or latency. <p>

    3. Maybe it occupies those 2% at times when it shouldn't be occupying them.

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