I am into a project where I need 2 establish communication between ADuc814(Master) and ADuc841(Slave). Master shud Receive data transmitted by Slave. I am unable to establish the comm. I feel there is no response 4rm slave as though master generates the clock and SS pin is low, slave does not response. Is it necessary that both master and slave should operate in same CLOCK?? For Hardware connection, MOSI, MISO, SCLK and SS pins of Master and Slave are connected. Foll is the code Master Code
#include <ADUC814.H> unsigned char Data[20]; //Store SPI Rx data in Memory void Uart_Tx(unsigned char AsciData); //Serial Tx sbit SS = 0xB5; void main() { char i; PLLCON = 0x00; //Core Clk = 16.6777MHz //////////baud 0f 4800//////// RCAP2H = -1; RCAP2L = 0x92; TH2 = -1; TL2 = 0x92; SCON = 0x50; T2CON = 0x34; ////////////////////////////// CFG814 = 0x01; // Enable P3.5,6,7 for SPI SPICON = 0x37; // Master, CPOH=1,CPOL=0 SS = 0; // Slave Select Enable for(i=0;i<20;i++) { SPIDAT = 0x00; // SPI Clock Generate while(!ISPI); ISPI = 0; Data[i] = (unsigned char)SPIDAT; } /////////Serial Tx SPI Data into UART////////// for(i=0;i<20;i++) { Uart_Tx(Data[i]); Uart_Tx('\n'); } ///////////////////////////////////////////// }
Slave Code, ADuC841
void main() { char i; SPICON = 0x24; // Slave, CPOH=1, CPOL=0 for(i=0;i<20;i++) { SPIDAT = 0x38; /*Transmit Dummy Data, Asci of '8' while(!ISPI); ISPI = 0; } }
Friendzzzz Please Help.........
SPI uses one master clock: derived from the master uC. There is no need to 'sync' the master & slave uC oscillators.
NOTE: Assuming that your slave is not radically below its minimum operational frequency, then the slave's internal state machine should be capable of shifting in the master's bits, using the master's clock signal.
You should identify what you have already done during your testing of the system...
Are you sure that the Master's MOSI is connected to Slave's MISO, etc? (double-check it).
Did you see the Master's clock on a scope? was it good?
Was the master's data also valid?
What did the slave's data look like?
Are your voltage levels okay? (Slave's thresholds consistent with Master's? --- I don't want to look up those device data-sheets just yet).
I do not know about AD, but for the SILabs uCs hardware SPI engines you connect MOSI to MOSI and MISO to MISO. That makes sense to me.
Erik
MOSI = Master OUT, Slave IN (Master to Slave data direction) MISO = Master IN, Slave OUT (Slave to Master data direction)
So unless the SILabs uCs have some sort of software control on the data direction, I'm guessing you might be mistaken.
Oh, I get it ... sorry! Yes. Erik. You are right. Thats what I meant.
The point is to make sure that the data direction is correct.
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