Hi,
There is an application note on using the interrupt vectors in C51 c programming for 8051. It goes like this-
unsigned int int_count; unsigned char second;
void timer0 (void) interrupt 1 using 2 { if (++int_count == 4000) { /* count to 4000 */ second++; /* second counter */ int_count = 0; /* clear interrupt counter */ } }
Can anyone explain what does that "using 2" at the end of the function denote?
I understand that interrupt 1 specifies that this is the ISR for interrupt number for timer0 overflow at adress 000Bh. Does the last keyword "using 2" denote the polling priority of the interrupt?
TIA, Mrunmoy
Please read the Keil C51 manual about the directives interrupt and using.
Hint: the 8051 has 4 core register banks at the base of data RAM.
"Does the last keyword "using 2" denote the polling priority of the interrupt?"
Read about interrupt priority on the so-called 8051 bible set: www.nxp.com/.../80C51_FAM_ARCH_1.pdf www.nxp.com/.../80C51_FAM_HARDWARE_1.pdf www.nxp.com/.../80C51_FAM_PROG_GUIDE_1.pdf
A last note: the interrupt priority is not decided by polling, but by a combinatorial priority encoder on the chip interrupt logic.
Johnny,
Not to be overly pedantic, since you clearly know your stuff, but the Intel MCS-51 manual always refers to the fixed priority-arrangement among interrupts that are enabled and whose IP registers settings match as a "polling" order.
The "bible" says something to the effect of the interrupt flags being latched on S5P2 of each machine cycle and then "polled" in a fixed order on the next to determine which interrupt is "accepted."
The interrupt flags are not actually polled (as in checked one by one) but sampled by the hardware. It will - in parallell - sample all interrupt flags to make it's decision which interrupt to take.
Thanks to all of you for your answers. But i need a simple answer for: what does that "using 2" does?
http://www.keil.com/support/man/docs/c51/c51_le_funcdecls.htm
http://www.keil.com/support/man/docs/c51/c51_le_regbankspec.htm
Not only is the answer in the manual. The answer is also more or less implied by one of the answer posts you have received.
As Jason Daniel noted, the 80C51 hardware manual refers to the interrupt servicing order inside a given priority set as polling. The manual description states that the interrupt source is decided upon a 'priority within level', and the vectoring is done in the next S5P2 after the sampling of the interrupt flags. That really does not seem to be a polling operation, but a priority encoding operation, that essentially is a chained logic evaluation done by combinatorial logic, instead of sequential logic. Actually, both are very similar operations, but the difference is not subtle.
Polling is a term that refers to a synchronous sequential interrogation of devices, like for example of a network master that interrogates all slave devices on the network for data to exchange. It is described in many instances as a sequential operation applied in software as opposed to a hardware 'parallel' priority encoding. It could also easily be done in hardware, using sequential logic or state machines, but it is actually much more expensive to do polling in hardware with several flipflops than it is to do a simple priority encoding with a few logic gates.
That's why I think that the intra-priority vectoring of the 8051 is actually a combinatorial logic operation, rather than a clocked sequential logic, in which case the use of the term 'polling' by the documentation was an unfortunate choice of term.
But I must declare that I have not seen the actual implementation of the original 80C51 core, so I am only stating my opinion based on common sense.
As Jason Daniel noted, the 80C51 hardware manual refers to the interrupt servicing order inside a given priority set as polling.
I think y'all have confoosed the OP TOTALLY.
He asked about 'using' and have gotten answers about priority.
Now, I am not one to releieve anyone from reading the manuals, and usually wouldd not answer this directly instead of posting Please read the manual, but the above answers compel me to do so.
using direct the compiler to use the specified register stack, if you do not know what a register stack is Please read the manual.
Erik
And the OP did get an answer to that question.
Jonny Doin immediately answered: "Hint: the 8051 has 4 core register banks at the base of data RAM."
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