ROMEN / ROMS1 and Chipselects

// Concerns: Use of ROMEN / ROMS1 and extending the number of Chip Selects.

Last week I unpacked my phyCore module and I've done some reading in manuals and forums. This raised some issues I can't seem to figure out. The board I'm using is the phyCORE-167HSE with ST10F269 processor
intern:
256kB flash,;
8 + 2kB GP-RAM
2kB IRAM;

Extern:
1MB flash on /CS0:
512kB RAM on /CS1
4kB UARTon /CS2
512kB RAM at /CS3
4kB Ethernet on /CS4

Default the controller boots from external ROM (EA connected to Ground). I would like to use the internal ROM as well (for code or data-storage, I'm aware that both in 1 device won't work (Keil app note138)). In the processor manual (page 26/184) there is a discription of how to enable the internal ROM (for the original story see Chapter 5.4 Flash Memory Configuration of the ST-manual):

Assume external ROM was mapped to 0x0 0000 - 0xF FFFF. When I enable the internal ROM the first part of the external memory would be replaced by internal (which is default available on location 0x00 ???), when code is running from this memory I can imagine weird thigs will happen. The processor uses a bit in ROMS1 to map the internal ROM after the first 32 kB of ROM. This way code performing the settings of the bits ROMS1 and ROMEN executing from the first 32 kB of External ROM will not be overwritten and Internal memory will be at location 0x1 0000 - 0x4 FFFF.

Now there is something unclear about what happens to the memory-map:
Do I end up with this ???
32 kB of External ROM
256kB of Internal ROM
736kB of External ROM
That's no use becausse there's a gap in the external memory configuration now, Instead of gaining memory I end up with the same amount...
Of course I could change the jumper setting and map internal memory from address 0 and external higher in the memory map, but isn't there a possibility to start up from another address than 0? I saw a description on how to accomplish this for the C51 family http://www.keil.com/support/docs/189.htm, but how is it done (if possible) with the ST10?


Then another totally different question:
On my phycore module all Chip selects are populated with external devices. However, I'd like to connect more devices to the data/address bus. Is it possible to extend the data bus with additional CS-signals by means of external logic? (e.g. I/O steered or an external address decoder). Can I reconfigure the BUSCON/ADDRSEL- registers after initialization? (after the EINIT command has been executed)


If anyone could be of assistance it would be greatly appreciated.

-Dirk

  • Hi Dirk,

    Do I end up with this ???
    32 kB of External ROM
    256kB of Internal ROM
    736kB of External ROM
    That's no use becausse there's a gap in the external memory configuration now, Instead of gaining memory I end up with the same amount...


    Yes, you end up with that. But there is a way around this problem. Configure the ADDRSELx registers in such a way that addresses 0..0x1FFFFF (the lowest 2M bytes) are assigned to CS0 (except for the ranges occupied by on-chip ROM, RAM and SFRs, naturally.) Now the thing is that you can access external ROM either via 0..0xFFFFF or via 0x100000..0x1FFFFF. That is because address line A20 is not connected to external ROM chip(s) so they don't care. So you can access the parts or external ROM overlapped by on-chip ROM via its 'mirror image' (0x100000..0x1FFFFF). This way no memory is wasted.

    Is it possible to extend the data bus with additional CS-signals by means of external logic? (e.g. I/O steered or an external address decoder).

    Yes, it is. Download a PDF from HITEX's website:
    http://www.hitex.com/pdf/166GUIDE.pdf
    It has a few tips on designing with C166, including info on address decoders.

    Can I reconfigure the BUSCON/ADDRSEL- registers after initialization? (after the EINIT command has been executed)

    Yes, you can.

    Regards,
    - mike

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