<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>LPC2148 with ENC28J60</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/35760/lpc2148-with-enc28j60</link><description> 
Hi 

 
I have connected LPC2148 with 12Mhz Crystal, 15 Mhz PCLK to
ENC28J60 with the following PIN Connections. 

 
ARM ENC28J60 
PO.4 &amp;gt;&amp;gt;&amp;gt;&amp;gt;&amp;gt; SCK 
PO.6 &amp;gt;&amp;gt;&amp;gt;&amp;gt;&amp;gt; SI 
PO.5 &amp;gt;&amp;gt;&amp;gt;&amp;gt;&amp;gt; SO 
PO.7 &amp;gt;&amp;gt;&amp;gt;&amp;gt;&amp;gt; CS 

 
RESET PIN of ENC28J60 is connected to hardware reset PIN</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: LPC2148 with ENC28J60</title><link>https://community.arm.com/thread/69652?ContentTypeID=1</link><pubDate>Mon, 12 Sep 2016 13:06:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:809994c7-533b-48da-baa8-07ad7194754f</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
No simulator provides a 100% fully accurate simulation - they all
have certain restrictions &amp;amp; limitations.&lt;/p&gt;

&lt;p&gt;
You might be using the simulator wrong, and/or not have it
configured correctly.&lt;/p&gt;

&lt;p&gt;
For specific details about the particular simulator and its
configuration, operation, and restrictions/limitations, you should
consult the &lt;b&gt;documentation&lt;/b&gt; for that simulator, and/or contact
the supplier for support; eg,&lt;/p&gt;

&lt;p&gt;
&lt;a href="https://www.labcenter.com/"&gt;https://www.labcenter.com/&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
&lt;a href="http://support.labcenter.co.uk/forums/"&gt;support.labcenter.co.uk/.../&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
Also, the simulation can only be as accurate as the information
you give it - so are you sure that you have 100% exactly and
completely modelled your precise hardware?&lt;/p&gt;

&lt;p&gt;
And, of course, the simulator will not simulate any faults or
errors in the hardware you are using.&lt;/p&gt;

&lt;p&gt;
As its name suggests, use the &lt;b&gt;Debugger&lt;/b&gt; to debug your real
hardware system ...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LPC2148 with ENC28J60</title><link>https://community.arm.com/thread/64985?ContentTypeID=1</link><pubDate>Mon, 12 Sep 2016 04:22:41 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1ed858d0-f3fa-47ff-a9bd-27f42fc62f2f</guid><dc:creator>cOSankalp Agarwal</dc:creator><description>&lt;p&gt;&lt;p&gt;
Is this a Proteus forum ?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: LPC2148 with ENC28J60</title><link>https://community.arm.com/thread/64986?ContentTypeID=1</link><pubDate>Thu, 08 Sep 2016 01:34:59 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d7914e4b-7c2c-4c00-8358-c84f636e1200</guid><dc:creator>Arun R</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;b&gt;ENC INIT&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
void enc28j60Init(uint8_t* macaddr)&lt;br /&gt;
{&lt;/p&gt;

&lt;p&gt;
ENC28J60_CONTROL_DDR |= ((1&amp;lt;&amp;lt;ENC28J60_CONTROL_CS)); IO1DIR =
0x01000000;&lt;/p&gt;

&lt;p&gt;
CSPASSIVE; // ss=0&lt;/p&gt;

&lt;p&gt;
IO1CLR = 0x01000000; delay_ms(200); IO1SET = 0x01000000;&lt;/p&gt;

&lt;p&gt;
PINSEL0 |= 0x1500; S0SPCCR = 0x0e; //0a 6.6m 0c 5.5m 0e 4.7m //
org 0e S0SPCR = 0x20;&lt;/p&gt;

&lt;p&gt;
delay_ms(400);&lt;/p&gt;

&lt;p&gt;
enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);&lt;/p&gt;

&lt;p&gt;
delay_ms(50);&lt;/p&gt;

&lt;p&gt;
NextPacketPtr = RXSTART_INIT;&lt;/p&gt;

&lt;p&gt;
// Rx start enc28j60Write(ERXSTL, RXSTART_INIT&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ERXSTH, RXSTART_INIT&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
// set receive pointer address enc28j60Write(ERXRDPTL,
RXSTART_INIT&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ERXRDPTH, RXSTART_INIT&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
// RX end enc28j60Write(ERXNDL, RXSTOP_INIT&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ERXNDH, RXSTOP_INIT&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
// TX start enc28j60Write(ETXSTL, TXSTART_INIT&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ETXSTH, TXSTART_INIT&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
// TX end enc28j60Write(ETXNDL, TXSTOP_INIT&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ETXNDH, TXSTOP_INIT&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(ERXFCON,
ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_PMEN);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(EPMM0, 0x3f);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(EPMM1, 0x30);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(EPMCSL, 0xf9);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(EPMCSH, 0xf7);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MACON1,
MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);&lt;/p&gt;

&lt;p&gt;
// bring MAC out of reset enc28j60Write(MACON2, 0x00);&lt;/p&gt;

&lt;p&gt;
// enable automatic padding to 60bytes and CRC operations
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3,
MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);&lt;/p&gt;

&lt;p&gt;
// set inter-frame gap (non-back-to-back) enc28j60Write(MAIPGL,
0x12);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAIPGH, 0x0C);&lt;/p&gt;

&lt;p&gt;
// set inter-frame gap (back-to-back) enc28j60Write(MABBIPG,
0x12);&lt;/p&gt;

&lt;p&gt;
// Set the maximum packet size which the controller will accept //
Do not send packets longer than MAX_FRAMELEN: enc28j60Write(MAMXFLL,
MAX_FRAMELEN&amp;amp;0xFF);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAMXFLH, MAX_FRAMELEN&amp;gt;&amp;gt;8);&lt;/p&gt;

&lt;p&gt;
// do bank 3 stuff // write MAC address // NOTE: MAC address in
ENC28J60 is byte-backward enc28j60Write(MAADR5, macaddr[0]);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAADR4, macaddr[1]);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAADR3, macaddr[2]);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAADR2, macaddr[3]);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAADR1, macaddr[4]);&lt;/p&gt;

&lt;p&gt;
enc28j60Write(MAADR0, macaddr[5]);&lt;/p&gt;

&lt;p&gt;
// no loopback of transmitted frames enc28j60PhyWrite(PHCON2,
PHCON2_HDLDIS);&lt;/p&gt;

&lt;p&gt;
// switch to bank 0 enc28j60SetBank(ECON1);&lt;/p&gt;

&lt;p&gt;
// enable interrutps enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE,
EIE_INTIE|EIE_PKTIE);&lt;/p&gt;

&lt;p&gt;
// enable packet reception enc28j60WriteOp(ENC28J60_BIT_FIELD_SET,
ECON1, ECON1_RXEN);&lt;/p&gt;

&lt;p&gt;
}&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>