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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Keil generating misaligned LDR?</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/35150/keil-generating-misaligned-ldr</link><description> 
On a Cortex M0: 

 
50: tmp=SST_PSI-&amp;gt;BANK[2].PERID //should be 0x40050000 

 
0x000006EA 480A LDR r0,[pc,#40] ; @0x00000714 

 
... 

 
0x00000712 1000 DCW 0x1000 
0x00000714 0000 DCW 0x0000 
0x00000716 4005 DCW 0x4005 
0x00000718 B5F0 PUSH {r4-r7,lr</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Keil generating misaligned LDR?</title><link>https://community.arm.com/thread/83060?ContentTypeID=1</link><pubDate>Thu, 25 Feb 2016 10:42:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1ba43449-c7c3-4e31-af77-291b7d9bfa40</guid><dc:creator>Danny Miller</dc:creator><description>&lt;p&gt;&lt;p&gt;
No, it&amp;#39;s +4, but I missed something:&lt;/p&gt;

&lt;p&gt;
&amp;quot;In Thumb state:&lt;br /&gt;
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the
address of the current instruction plus 4 bytes.&lt;br /&gt;
For all other instructions that use labels, the value of the PC is
the address of the current instruction plus 4 bytes, with bit[1] of
the result cleared to 0 to make it word-aligned.&amp;quot;&lt;/p&gt;

&lt;p&gt;
OK, that&amp;#39;s a bit different then. The assembly is 16-bit
instructions so we&amp;#39;re talking Thumb-16.&lt;/p&gt;

&lt;p&gt;
So for:&lt;br /&gt;
0x000006EA 480A LDR r0,[pc,#40] ; @0x00000714&lt;/p&gt;

&lt;p&gt;
That would be 0x6ea+#4, then clearing Bit [1] (I missed that part)
gets 0x6EC for the effective program counter. 0x6EC + #40 would be
0x714, which would be the correct target, and aligned.&lt;/p&gt;

&lt;p&gt;
Still leaves me with a problem here, just not what I thought.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Keil generating misaligned LDR?</title><link>https://community.arm.com/thread/64541?ContentTypeID=1</link><pubDate>Wed, 24 Feb 2016 21:44:47 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b26ee26e-8b14-4ad7-9263-b993a61280f1</guid><dc:creator>Westonsupermare Pier</dc:creator><description>&lt;p&gt;&lt;p&gt;
The encoding looks legitimate using non-Keil tools&lt;/p&gt;

&lt;pre&gt;
000006EA 480A                      ldr     r0, [pc, #40]   ; (&amp;#36;000714)
&lt;/pre&gt;

&lt;p&gt;
It&amp;#39;s a 16-bit opcode, so I&amp;#39;m pretty sure it is pc + 2 + 40&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>