I was reading up on the flash eeprom and best I can tell for the stm32f chips this is needed. micromouseusa.com/
Has Keil mdk5 not provided a simple function?
hmm, same errors as my post on 22-Aug-2017 15:28
Many definitions missing. I tried to included #include "stm322xg_eval.h" but it is not found and also not included in the example download.
The RTC has 80 bytes of backup registers, as I recall.
The BKPRAM (NVRAM) has 4KB
Ok thx, one thing before I start this journey. Is this example only going to get me the 80 bytes? I read the RTC only had 80 and the other (more battery drain) had more.
"Get Software", bottom of the page gets you to the software examples Andrew and I have worked with. www.st.com/.../stsw-stm32062.html
I don't see the example in C:\Keil_v5\ I normally use the pack installer and I don't see it in there either. Anyone have a link to the example. I can't find it searching the net.
The linked Stack Overflow thread specifically states that it uses STM32F4xx_DSP_StdPeriph_Lib - which is clearly not the one for STM32F2...
I have STM32F2xx_StdPeriph_Lib_V1.1.0 to hand.
It does, indeed, have a Backup Domain example - in Project\STM32F2xx_StdPeriph_Examples\RTC\BKP_Domain
Yes, it is important to know (at least for you to know) what ST libraries you are using, assuming that you are in fact using some. There is the STM32F2xx_StdPeriph_Lib of which the example you posted uses. It fully supports the STM32F205. There is also the STM32F2xx_HAL_Driver?
Surely, ST provide examples of how to do this for the specific chip that you have?
Guessing ill have to convert this to 205. I had to fix the implicit declarations with prototypes.
static void RCC_AHB1PeriphClockCmd(char, bool); static void RCC_APB1PeriphClockCmd(char, bool); static void PWR_BackupAccessCmd(bool); static void PWR_BackupRegulatorCmd(bool);
but the following are unknown to the 205 RCC_AHB1Periph_BKPSRAM RCC_APB1Periph_PWR
Guessing the 205 has different naming and possibly different address ranges. The data sheet shows AHB1 with a BKPSRAM perf but these are unknown to the IDE. Do I have to enable this in RTE or add an include.
Yes, although I think calling it NVRAM will be more inline with what it is.
is this what I need? stackoverflow.com/.../how-to-use-backup-sram-as-eeprom-in-stm32f4
Yes that may have been the section that game us the clue that eeprom was available. In our situation a battery would work. If enabled in code, could eeprom be read and written to in the normal convention )(via a command)?
Bit weaselly, the data sheet doesn't talk about EEPROM. Must have been losing sails* because the keyword "EEPROM" wasn't hitting on the parametric search.
EEPROM doesn't need batteries, ST has an emulation library using FLASH.
The NVRAM/BKPRAM is within the MPU address space, if the OP has a battery and is comfortable with using that, then map a structure within the NVRAM, copy stuff in/out, or add it to a scatter file.
*beats detector
It does avoid pretending it is EEPROM and treats it like FLASH, so it does dispense with a rather thick abstraction from ST with an Adddress/Byte storage system that immediately reduces the available space by at least a quarter.
The problem with pretending is that you keep doing things which are inappropriate rather than change the paradigm to a more appropriate one. ie a FLASH within the MPU address space, vs a I2C EEPROM
Sorry I was not clear on that.
I have a st32f205 with eeprom on the chip, I simply just want to write and read form it. This "emulating EEPROM" is confusing me. Is there no easy way to write/read to eeprom on the chip. All the info I find talks about this "emulating EEPROM" when searching for how to use the eeprom.
I see 1 reference to EEPROM in the STM32F20xxx manual. It this what you are talking about using?
Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the following: • Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 day of the month. • Programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. • It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal lowpower RC oscillator or the high-speed external clock divided by 128. The internal lowspeed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. • Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. • A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 3.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin.
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