bug report: CMSIS Driver I2C STM32, I2C_CR1_POS

Hello,

Driver: CMSIS I2C STM32F4xx, Rev 2.3

The Driver produces an error after a 2-byte Master Receive Operation.

After a 2-byte master Receive Operation I2C_CR1_POS bit remains set.
A following master receice operation with more than 2 Bytes will Crash.
The closing of the receive progress is faulty due to the POS bit.
No NACK is generated. (A deadlock is possible if the last bit of read data was zero.
In this case the slave device holds sda low, waiting for clock pulses. Master can not generate stop condition.
MSL bit in SR2 remains set.)

Error stimulation Code:
I2C1_MasterReceive (0x50, &buffer, 2, 0);
I2C1_MasterReceive (0x50, &buffer, 3, 0);

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