Driver: CMSIS I2C STM32F4xx, Rev 2.3
The Driver produces an error after a 2-byte Master Receive
After a 2-byte master Receive Operation I2C_CR1_POS bit remains
A following master receice operation with more than 2 Bytes will
The closing of the receive progress is faulty due to the POS bit.
No NACK is generated. (A deadlock is possible if the last bit of read
data was zero.
In this case the slave device holds sda low, waiting for clock
pulses. Master can not generate stop condition.
MSL bit in SR2 remains set.)
Error stimulation Code:
I2C1_MasterReceive (0x50, &buffer, 2, 0);
I2C1_MasterReceive (0x50, &buffer, 3, 0);
Actually POS bit handling and 3 byte reception have issues. But
this can be quickly fixed in I2C_EV_IRQHandler:
- POS should be cleared after receive of the last two bytes
- XFER_CTRL_WAIT_BTF flag should be set after ADDR flag is cleared
and number of bytes to receive is 3
A updated driver version including a fix for this problem can be
Tanks for your effort.
There is similar bug in ver. 2.6
Driver doesn't clear I2C_CR1_POS after 2-byte reception in DMA
mode. There is no problem when DMA is not used.
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