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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>About PCLK</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/34185/about-pclk</link><description> 
Hi, 

 
I have bought a LandTiger development board for LPC1768. it has a
12Mhz Xtal on it. I am trying to use its USART0 and I need to know
PCLK. is it 3MHz? I devide 12 by 4. am I right? 
 </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/148519?ContentTypeID=1</link><pubDate>Sun, 18 Jan 2015 07:29:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f68050f1-10fc-4d84-980b-c27dd240d2ea</guid><dc:creator>mohammad bidmeshki</dc:creator><description>&lt;p&gt;&lt;p&gt;
Try and error!? why? reading of the user manual is not more
difficult than try and error. if you realize the structure of the PLL
and clock section, you can set the desired baud rate with 0% error.
in edition there is a configuration wizard in start up file that you
can manage the system clock if you add it to your project.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/148321?ContentTypeID=1</link><pubDate>Sat, 17 Jan 2015 02:44:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7e495faa-29b5-48d5-8051-89661f8dff0c</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
By try and error (I mean by using a for() loop) I found that the
best values for DLL is 0x5 and for FDR is oxf5.&lt;br /&gt;
by these values USART0 works well for Baudrate 9600. But my problem
is not solved since I dont know how to config for other values of
Baudrate!!! I need your kind help.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/147928?ContentTypeID=1</link><pubDate>Sat, 17 Jan 2015 02:13:59 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1423e7a3-42e4-4583-873f-718b500a2173</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
I think I have not set a proper value in FDR register. Do you have
any idea how to set it? I dont understand what is the devideVAL[3:0]
and mulVal[7:4]??&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/147095?ContentTypeID=1</link><pubDate>Sat, 17 Jan 2015 01:02:59 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e2c6792a-ce7e-45cd-923e-1e79f519fdde</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi,&lt;/p&gt;

&lt;p&gt;
you are right. I had the mistake. I followed your notes with
M=12,N=1 and found DLL=117 or 0x75.&lt;br /&gt;
But I don&amp;#39;t receive any character in PC unless I give a value between
1 and 40 for DLL so I receive sth like ????? .&lt;br /&gt;
It is confusing!&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/145629?ContentTypeID=1</link><pubDate>Fri, 16 Jan 2015 10:15:51 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:315105ef-e8dd-4eed-928b-09232d629f5c</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
I take it you haven&amp;#39;t actually downloaded the PLL spreadsheet from
NXP:s site?&lt;br /&gt;
And you didn&amp;#39;t try my formula either.&lt;/p&gt;

&lt;p&gt;
PLL0 = 2 * M * FOSC / N = 2 * 10 * 12 / 2 = 120MHz.&lt;br /&gt;
But the datasheet &amp;sect;5.1 says the PLL0 requires a frequency 275 -
550 MHz. 120MHz is much too low.&lt;/p&gt;

&lt;p&gt;
Change M = 12&lt;br /&gt;
Change N = 1&lt;br /&gt;
Then you get PLL0 = 2*12*12/2 = 288MHz.&lt;/p&gt;

&lt;p&gt;
With CPUDIV = 4, you then get CCLK = PLL0/4 = 288/4 = 72MHz&lt;/p&gt;

&lt;p&gt;
With PCLK_DIV = 4, you then get PCLK = CCLK/4 = 72/4 = 18MHz.&lt;/p&gt;

&lt;p&gt;
Then compute a suitable baudrate divisor to get your required
baudrate.&lt;/p&gt;

&lt;p&gt;
Or select a different set of M, N, CPUDIV and run the CCLK at a
different speed - if I remember correctly, some LPC17xx manages
100MHz and some manages up to 120MHz.&lt;/p&gt;

&lt;p&gt;
If you need really high UART baudrates, you might consider to use
a lower PCLK_DIV to not get too large baudrate error from rounding
error when computing the baudrate divisor - but that also depends on
how high CCLK you configure.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/143568?ContentTypeID=1</link><pubDate>Fri, 16 Jan 2015 09:30:31 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2a483fe4-c23f-4e27-b709-88211a2fea0c</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi&lt;/p&gt;

&lt;p&gt;
I could see some unknown characters received in PC from USART0 of
LPC1768. I know my DLL is not set well.&lt;br /&gt;
I know I should give an exact DLL. my Xtal is 12 MHz. and other
values are:&lt;/p&gt;

&lt;p&gt;
OSCRANGE=1 to 20 Mhz&lt;br /&gt;
SLKSRC: Main Ocilator&lt;br /&gt;
PLL0 multiplier selection: M=10&lt;br /&gt;
PLL0 Divider selection: N=2&lt;br /&gt;
CCLKSEL: divide value for CPU clock from PLL0 :4&lt;br /&gt;
USART0: PCLK=CCLK/4&lt;/p&gt;

&lt;p&gt;
How can I find CCLK?&lt;/p&gt;

&lt;p&gt;
so that I find PCLK and get DLL from it.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/140806?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 05:56:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:4fd3126a-8b9c-42c2-b6d2-b444fbed2569</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Without oscilloscope you can always use a blinking LED with a
timer or similar to verify your frequencies. Or if you have a
multimeter with frequency measurement, you can have your UART send
suitable characters and let the multimeter tell how many
pulses/second it sees.&lt;/p&gt;

&lt;p&gt;
Or run the UART without handshake and check how many
characters/second it can send when you keep the transmit FIFO always
non-empty.&lt;/p&gt;

&lt;p&gt;
Note that NXP has an Excel spreadsheet with a lot of different
PLL0 values where you enter your FOSC frequency and then can see the
outcome of PLL frequency and resulting CCLK with different M, N and
CPU divisor. And when you then have figured the settings to get a
suitable CCLK, it&amp;#39;s trivial to get the PCLK based on what PCLK
divisor value you decide to set.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/131478?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 05:35:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d45019a9-6eae-4873-a108-7aacc36050ce</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
I don&amp;#39;t have oscilloscope here. I tried different values for DLL
but no character appears in the PC. I am sure about the connection
coz I have tested serial port by another device.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/128819?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 04:22:35 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b3bdba6c-f6bc-415a-84b7-820c4a8831e7</guid><dc:creator>Charlie Hebdo</dc:creator><description>&lt;p&gt;&lt;p&gt;
Doesn&amp;#39;t work, or works at a different speed than expected?&lt;/p&gt;

&lt;p&gt;
So if you output a stream of characters (0x55) from UART0, and you
review the signal on an oscilloscope what bit timing do you actually
observe?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/117704?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 02:54:06 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:30d8df5f-7731-4d5d-8b43-7e1b33311a10</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
Dear Arrogant,&lt;/p&gt;

&lt;p&gt;
yes it is really large value for PLL0. I changed MSEL from 100 to
10. and NSEL is 6.&lt;br /&gt;
therefore PLL0_clk=(2*10*12MHz)/6 which will be 40MHz.&lt;br /&gt;
So that CCLK=10MHz&lt;br /&gt;
PCLK=(CCLK/4)=2.5 MHz&lt;/p&gt;

&lt;p&gt;
there for DLL= 2.5MHz/(16*9600) = 16.27 which is approximately
0x10&lt;br /&gt;
I entered this in my code but USART0 is not working!&lt;/p&gt;

&lt;pre&gt;
void SER_init (int uart) {
  LPC_UART_TypeDef *pUart;
                              /* UART0 */
    LPC_PINCON-&amp;gt;PINSEL0 |= (1 &amp;lt;&amp;lt; 4);
    LPC_PINCON-&amp;gt;PINSEL0 |= (1 &amp;lt;&amp;lt; 6);

    pUart = (LPC_UART_TypeDef *)LPC_UART0;


   pUart-&amp;gt;LCR    = 0x83;                          /* 8 bits, no Parity, 1 Stop bit  */
   pUart-&amp;gt;DLL    = 0x10;                             //BR=9600
   pUart-&amp;gt;FDR    = 0x21;                          /* FR 1,507, DIVADDVAL = 1, MULVAL = 2 */
   pUart-&amp;gt;DLM    = 0;                             /* High divisor latch = 0         */
   pUart-&amp;gt;LCR    = 0x03;                          /* DLAB = 0                       */
}
&lt;/pre&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/108053?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 02:02:28 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:56853185-afe2-4e15-a373-035a7839a78c</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
PLL0_clk = (2 * M * FOSC) / N&lt;/p&gt;

&lt;p&gt;
And CCLK is then the result of dividing PLL0_clk with a divider in
CCLKSEL.&lt;/p&gt;

&lt;p&gt;
It seems strange to have a PLL0 running at 100 times FOSC for a
12MHz FOSC, since 100*12MHz would be 1.2GHz and the PLL0 may not run
faster than 550MHz.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/82360?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 01:32:55 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a7a3a67a-4458-4806-b496-f7a55e1a0318</guid><dc:creator>Hamed Adldoost</dc:creator><description>&lt;p&gt;&lt;p&gt;
Indeed I did not pay attention to the system_lpc17xx.c file where
all the clock selection are listed.&lt;br /&gt;
I see some values let me add it here:&lt;br /&gt;
OSCRANGE=1 to 20 Mhz&lt;br /&gt;
OSCEN enabled&lt;br /&gt;
SLKSRC: Main Ocilator&lt;br /&gt;
PLL0 multiplier selection: 100&lt;br /&gt;
PLL0 Divider selection: 6&lt;br /&gt;
CCLKSEL: divide value for CPU clock from PLL0 :4&lt;br /&gt;
USART0: PCLK=CCLK/4&lt;br /&gt;
PCON USART0 enabled.&lt;/p&gt;

&lt;p&gt;
I dont understand what (divider selection=6) is!?&lt;/p&gt;

&lt;p&gt;
is cpu clock 120Mhz? (100*12Mhz).&lt;br /&gt;
is PCLK=120Mhz/4=30Mhz ?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: About PCLK</title><link>https://community.arm.com/thread/69041?ContentTypeID=1</link><pubDate>Wed, 14 Jan 2015 00:27:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6c3ab3a8-a574-40cd-bcf7-911df397c127</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Any reason why you run the processor so extremely slow - are you
running on batteries?&lt;/p&gt;

&lt;p&gt;
The 12MHz crystal is normally first upscaled by a PLL so you might
get a CCLK of 100MHz or something like that. But let&amp;#39;s say the PLL is
configured to scale the FOSC = 12MHz crystal giving a CCLK of 60MHz.
Then a division by four would give the UART a PCLK of 60/4 =
15MHz.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>