<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>understanding the SBUF register</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/32718/understanding-the-sbuf-register</link><description> 
The 8051 has only single SBUF register. 
But the datasheet say it can support full duplex. for full duplex
communication we must have different buffers(?) for transmitting and
receiving. 
how a single byte SBUF register work as two registers ? 

 
from</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/137199?ContentTypeID=1</link><pubDate>Tue, 10 Feb 2015 01:27:31 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:aee1d059-0e7a-470a-9771-32a865735de3</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
If &amp;quot;we&amp;quot; can implement full duplex depends on the skills &amp;quot;we&amp;quot;
have.&lt;/p&gt;

&lt;p&gt;
When implementing full duplex code, it doesn&amp;#39;t matter if the
processor has separate addresses for read and write data registers,
or if the read-only receive register shares address with the
write-only transmit register.&lt;/p&gt;

&lt;p&gt;
Full duplex is just a question of picking up received characters
when the processor flags received data as available, and giving the
UART more characters when the processor flags that the UART has room
for more outgoing characters. Then it&amp;#39;s just a question of selecting
polling code or making use of interrupts. And if the code should
contain some robust round-robin buffers so the main loop doesn&amp;#39;t have
to be 100% in lock-step with the speed the UART can handle individual
characters.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/128840?ContentTypeID=1</link><pubDate>Tue, 10 Feb 2015 01:16:40 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:9815f0eb-db39-418a-b771-7ec763e11d7b</guid><dc:creator>Kunchala Anil</dc:creator><description>&lt;p&gt;&lt;p&gt;
The Problem with so called Bible we have to go through number of
times to barely Understand it for begineers like me.&lt;/p&gt;

&lt;p&gt;
the 8051 UART is capable of Full duplex system.. But can we really
implement full duplex on it?&lt;br /&gt;
any code examples is very useful.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/69069?ContentTypeID=1</link><pubDate>Mon, 09 Feb 2015 13:17:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c4c9689e-39da-4060-943e-59d52a4755ac</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
... think about how &lt;b&gt;utterly &lt;i&gt;useless&lt;/i&gt;&lt;/b&gt; it would be if
reading SBUF did just give back the last value written to it!!&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/93336?ContentTypeID=1</link><pubDate>Mon, 09 Feb 2015 00:39:45 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:15848fa8-ddaa-44d5-8e74-7c1128a49a2c</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Having a read-only + a write-only register on top of each other is
quite common. Why create separate data-write and data-read registers
when a single &amp;quot;data&amp;quot; register works so well? And what action should
the processor then take if someone reads from the write-only register
or writes to the read-only register? Adding lots of extra transistors
just to cover the corner cases of giving users separate read and
write registers?&lt;/p&gt;

&lt;p&gt;
Another issue here is that there are often not even a 8-bit +
8-bit buffer &amp;quot;hidden&amp;quot; behind that data registers. On send, it&amp;#39;s
common to be at least two 8-bit registers. One for the data that gets
latched and shifted out and then one other where the program stores
the next byte to shift out.&lt;/p&gt;

&lt;p&gt;
And on read it&amp;#39;s the same thing. One buffer that shifts in new
data and one buffer where the program can pick up the last received
byte.&lt;/p&gt;

&lt;p&gt;
Step up to an improved processor, and send and receive might
suddenly get 16-byte FIFO - one in each direction. And accessed
through the same 8-bit read + 8-bit write registers overlapping the
same address. SBUF isn&amp;#39;t a memory cell. It&amp;#39;s the interface to a pipe.
And the pipe might contain lots if incomming and outgoing data. And
what has been dropped off for transmission can&amp;#39;t be peeked at again -
unless you are at the other side of the pipe where the data will
normally arrive some time later.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/69066?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2015 12:15:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8aea449a-e6e8-48d5-8cdd-a75e5d94ce77</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Is that true?&lt;/p&gt;

&lt;p&gt;
Even if it does happen to be true for the very limited case of the
basic, original Intel 8051, it is by no means rare nor unusual!&lt;/p&gt;

&lt;p&gt;
It is quite common to have hardware registers where Read &amp;amp;
Write perform different functions - so better get used to it!&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/120504?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2015 11:56:39 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f20eb706-4581-448c-9e9d-a3de3c2a52c8</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Time to study the so-called &amp;quot;bible&amp;quot; for the 8051 - a copy is
archived for reference here:&lt;/p&gt;

&lt;p&gt;
&lt;a href="http://www.danlhenry.com/mfg/philips/docs/80C51_FAM_ARCH_1.pdf"&gt;www.danlhenry.com/.../80C51_FAM_ARCH_1.pdf&lt;/a&gt;&lt;br /&gt;

&lt;b&gt;&lt;a href="http://www.danlhenry.com/mfg/philips/docs/80C51_FAM_HARDWARE_1.pdf"&gt;www.danlhenry.com/.../80C51_FAM_HARDWARE_1.pdf&lt;/a&gt;&lt;/b&gt;&lt;br /&gt;


&lt;a href="http://www.danlhenry.com/mfg/philips/docs/80C51_FAM_PROG_GUIDE_1.pdf"&gt;www.danlhenry.com/.../80C51_FAM_PROG_GUIDE_1.pdf&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
Specifically, look at the &lt;b&gt;Standard Serial Interface&lt;/b&gt; section
(starting on page 9) in the &lt;b&gt;80C51 Family Hardware
Description:&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
&lt;a href="http://www.danlhenry.com/mfg/philips/docs/80C51_FAM_HARDWARE_1.pdf"&gt;www.danlhenry.com/.../80C51_FAM_HARDWARE_1.pdf&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
And, in particular, look at the block diagrams in &lt;b&gt;Figures 15 -
16:&lt;/b&gt; where you can clearly see the two SBUF registers - one with
only Read access from the &amp;quot;80C51 Internal Bus&amp;quot;; the other with only
Write access (look at the directions of the arrows).&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/118593?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2015 08:03:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:be6e9f27-3188-4f5c-a642-654fe47980ae</guid><dc:creator>Westonsupermare Pier</dc:creator><description>&lt;p&gt;&lt;p&gt;
It&amp;#39;s a pair of peripheral registers, implemented with different
latches and logic, stop thinking of it as a RAM memory.&lt;/p&gt;

&lt;p&gt;
There are likely more than 16 flip-flops involved&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/82395?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2015 07:46:27 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c4f0271f-90ce-44d3-903a-917f04619987</guid><dc:creator>Kunchala Anil</dc:creator><description>&lt;p&gt;&lt;p&gt;
so SBUF is a 8 bit buffer which can actually store 16 bits?&lt;/p&gt;

&lt;p&gt;
8 bits for read only buffer&lt;br /&gt;
another 8 bits for write only buffer?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: understanding the SBUF register</title><link>https://community.arm.com/thread/69067?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2015 06:59:40 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:423fa7ed-1e99-44bc-82a9-b75167bdcb7d</guid><dc:creator>edPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
&amp;quot;how the single buffer register act as two?&amp;quot;&lt;/p&gt;

&lt;p&gt;
The failed assumption here is that you think there is &amp;quot;the single
buffer&amp;quot;&lt;/p&gt;

&lt;p&gt;
Writing to SBUF writes to one buffer.&lt;br /&gt;
Reading from SBUF reads from another buffers.&lt;br /&gt;
Wasn&amp;#39;t that very clearly described in the quoted text?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>