Hello everyone ,I am working with a board based on S3C2440A .
I am trying to transmit datas & commands from S3C2440A to a FRAM_CHIP hang on the S3C2440A' SPI_bus. I find that S3C2440 only have 8 bit spi_bus_width. But in fact I need the flow of bits to be continuously at least in a 32 bits. I know that some chips such as S5PC100 have 8-32 spi_bus_width,how can I make it with S3C2440?
The follow is the code I did,and there was a interval between each flow of 8bit when I observe the SPIMOSI0 & SPICLK signal with oscilloscope.
extern void inline TxSPI0_Byte(U8 data) { rSPTDAT0=data; while(!(rSPSTA0&0x01));//wait until Tx/Rx ready } extern void WrMemStatReg(unsigned char data) //CMD to operate FRAM { SPICS_LOW; //FRAM CS ON TxSPI0_Byte(WRSR_CMD);//wave A --8bit TxSPI0_Byte(data); //wave B --8bit SPICS_HIGH; } wave A and wave B are not continuously
Somebody help me? Still waiting ...
What are you waiting for?
That people who doesn't use your processor will spend their payed worktime to retrieve the datasheet for your processor and read all there is about the SPI functionality?
Have you considered what happens if you run the slave-select signal manually? Then you can run any number of 8-bit transfers before you restore the slave-select. A synchronous protocol like SPI don't care if there is a bit of extra delay every 8 bits as long as the total data stream manages to transfer data fast enough for the intended use case.
Thanks for your suugestion .I have considered your suggestion. It must be a good idea in some situations that the slave can be transform to a host, but the FRAM can not be a host, I have to simulate a SPI clk artificially,and the SPI controller lost its significance,and I have to trans/recieve data all by my self. Are you agree with me?
I have considered your suggestion. It doesn't look like you did, because nobody suggested anything even remotely like your next statement: It must be a good idea in some situations that the slave can be transform to a host,
Nobody said anything about switching the roles of SPI master and slave.
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