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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/32054/why-r0-and-r1-for-indirect-addressing</link><description> 
Why do we use R0 and R1 in indirect addressing mode of 8051? This
question has been answered in one of the threads but i want to know
how come 8051 can only select one bit for R0 or R1 and R2 to R7 is
not possible. sorry if i sound a little stupid.</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/128305?ContentTypeID=1</link><pubDate>Fri, 13 Sep 2013 00:25:03 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a39a0c93-f309-4068-9889-afdfbf32a10f</guid><dc:creator>Modulated Symbol</dc:creator><description>&lt;p&gt;&lt;p&gt;
Thank you Erik. The documents really helped a lot. a very helpful
document indeed. Thanks again :)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/128289?ContentTypeID=1</link><pubDate>Thu, 12 Sep 2013 21:44:46 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:77ea569d-0a25-444d-a942-48d91d06a2df</guid><dc:creator>Ash J</dc:creator><description>&lt;p&gt;&lt;p&gt;
To understand why instructions are designed in such formats, you
need to study how the hex codes (for the respective opcodes) are
designed/encoded in any processor/controller. Each instruction bit
(or a group of bits) specify the operation, source, destination etc
info.&lt;br /&gt;
_look at the &amp;quot;encoding&amp;quot; specified for each instruction in files
referred by Erik_&lt;/p&gt;

&lt;p&gt;
PS: Dont bother that much about _why is it designed in such a
way?_ In engineering, each design has a lot of reasons, and a lot of
smart people out there have worked to design it as it is.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/120144?ContentTypeID=1</link><pubDate>Thu, 12 Sep 2013 05:52:58 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2229af9f-4095-45d4-b85f-70aa2993d2b7</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
I guess you didn&amp;#39;t pick up the hint from my original post where I
asked &amp;quot;Are you debating why Intel designed the processor instruction
set as they did, trying to cram in so [sic!] much information as
possible in a byte&amp;quot;.&lt;/p&gt;

&lt;p&gt;
They used about 50000 transistors for the complete processor
including timers etc. And the instruction set really has to look
different when you try to figure out what to store in one byte (8
lonely bits) compared to a processor who reads 32-bits as minimum
size from the memory.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/117384?ContentTypeID=1</link><pubDate>Thu, 12 Sep 2013 05:30:44 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:3fe86c24-4de9-4a6c-8442-28e24505889c</guid><dc:creator>H Matherson</dc:creator><description>&lt;p&gt;&lt;p&gt;
Look at the instruction encoding for the instructions that specify
indirect addressing.&lt;/p&gt;

&lt;p&gt;
You&amp;#39;ll see that only one bit is available for specifying the
register to be used.&lt;/p&gt;

&lt;p&gt;
It is difficult to get a selection of more than two registers when
only one bit is available for that specification.&lt;/p&gt;

&lt;p&gt;
The 8051 has, as far as I&amp;#39;m aware, never been described as being
orthogonal.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/107273?ContentTypeID=1</link><pubDate>Thu, 12 Sep 2013 04:33:57 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:833785e4-1df1-48b0-81d4-9b3fbfa9b43e</guid><dc:creator>Modulated Symbol</dc:creator><description>&lt;p&gt;&lt;p&gt;
LOL i have no problems. I have recently started studying 8051 and
I am geek in this domain. I have seen examples where data has been
loaded into bank registers (R0, R1, R2.... and so on). all these
registers are 8 bit registers and are located one above the other in
memory. i wanted to know if we can use other registers (R2, R3,...and
so on) for data storage then what is the reason behind not using
R2-R7 for register indirect addressing? if its because of the
internal architecture of 8051 then i would like to know what&amp;#39;s so
different with registers R2-R7 that they can not be used for register
indirect addressing mode. Thanks in advance&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/84875?ContentTypeID=1</link><pubDate>Thu, 12 Sep 2013 00:19:22 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:84a89cfa-4581-4c1e-9e52-d93b8ac10f38</guid><dc:creator>garaf tuyen</dc:creator><description>&lt;p&gt;&lt;p&gt;
Sorry buddy, but the obtaining of benefits with what was posted
above is a bad idea.&lt;br /&gt;
maybe I didn&amp;#39;t say that I have with the language problem (very
conceal myself&lt;br /&gt;
whenever possible to see they were at the elementary sense), but
(here I cuss) this too.&lt;/p&gt;

&lt;p&gt;
I and others here also started (I&amp;#39;m still here I don&amp;#39;t really
understand) what you must do with R0 and R1. but I fit into the core
framework of local processing rules, and you, it seems they march it.
I warn you - if you&amp;#39;ll use C51 (or my friends), you are certainly
reward (free translation).&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/81422?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 23:16:30 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e15c3a64-78de-4ddd-ab2c-f75d0afcfd27</guid><dc:creator>Ash J</dc:creator><description>&lt;p&gt;&lt;p&gt;
The compiler uses only R0 &amp;amp; R1 because hardware is designed
such that only R0 &amp;amp; R1 can be used.&lt;/p&gt;

&lt;p&gt;
Its our design and we dont like numbers 2-7, hence we designed
only for R0 &amp;amp; R1. &lt;b&gt;Do you have any problem with that?&lt;/b&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Why R0 and R1 for indirect addressing?</title><link>https://community.arm.com/thread/68355?ContentTypeID=1</link><pubDate>Wed, 11 Sep 2013 07:31:13 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7cdf55c3-5111-4a23-a7fa-d4d272ed0516</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Are you debating why Intel designed the processor instruction set
as they did, trying to cram in so much information as possible in a
byte, or why the compiler generates code in a specific way?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>