SSP1 of LPC1768

I have two question on SSP1 of LPC1768

1. We have configured SSP1 as TI SSI for receiving 16 bits of data. We have connected Sclk pin to Clock of salve and MISO pin to Data pin of Slave.We have generated clock to receive data from our slave. If i send the clock then SPDR value is getting updated but RNE bit is not set thus we are not able to read SPDr value. If we send the clock again my SPDR is always 0.

2. Can we read 18 bit data from the SSP1 which is configured as TI SSI with DSS as 9 bit and receiving SPDR value twice.

Code:

int main()
{
          int j;

           SystemInit();

           SSP1Init();
           LPC_SSP1->DR=0x0000;
           SSPSend(1,0x0000,16);


          while(1)
          {


     }
 }

void SSP1Init( void )
{
    uint8_t i, Dummy=Dummy;
    LPC_SC->PCONP |= (0x1<<10);/* Enable AHB clock to the SSP1. */
    LPC_SC->PCLKSEL0 &= ~(0x3<<20);
     /* P0.6~0.9 as SSP1 */
    LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<16)|(0x3<<18));
    LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<16)|(0x2<<18));


/* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */ LPC_SSP1->CR0 = 0x075F; /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ LPC_SSP1->CPSR = 0x2; for ( i = 0; i < FIFOSIZE; i++ ) { Dummy = LPC_SSP1->DR; /* clear the RxFIFO */ } NVIC_EnableIRQ(SSP1_IRQn); /* Enable the SSP Interrupt */
LPC_SSP1->CR1 = SSPCR1_SSE;/* Master mode *//* Device select as master, SSP Enabled */
/* Set SSPINMS registers to enable interrupts */ /* enable all error related interrupts */ LPC_SSP1->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM; return; }

void SSPSend( uint32_t portnum, uint16_t buf)
{
  uint32_t i;
  uint16_t Dummy = Dummy,receive[9];
      if ( portnum == 1 )
        {
          /* Move on only if NOT busy and TX FIFO not full. */
          while ( (LPC_SSP1->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF );
          LPC_SSP1->DR = buf;
          //buf++;
    #if !LOOPBACK_MODE
          while ( (LPC_SSP1->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );

          LPC_SSP1->DR=0x0000;
          receive[0] = LPC_SSP1->DR;
#else
          /* Wait until the Busy bit is cleared. */
          while ( LPC_SSP1->SR & SSPSR_BSY );
#endif
    }

  return;
}

Parents
  • The chip has a FIFO. If you configure for 9-bit transfers then you need to perform two reads to pick up an 18-bit transfer and then merge the two reads into an 18-bit value in your own code.

    But I don't understand your question since your sentences doesn't seem to agree with your code. You mentions TI SSI, but then your code contains a comment

    /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
    LPC_SSP1->CR0 = 0x075F;
    

    The assign seems to be a mixture between SPI and TI SSI.

    Next thing here is that you talk about having connected 2 wires between processor and your slave device. For two-way communication you should have 4. But what about your FS signal?

    Another thing is that if not in loopback mode you have two sends but one receive:

    LPC_SSP1->DR = buf; <= send
    while ( (LPC_SSP1->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
    
    LPC_SSP1->DR=0x0000; <= send
    receive[0] = LPC_SSP1->DR; <= receive
    

Reply
  • The chip has a FIFO. If you configure for 9-bit transfers then you need to perform two reads to pick up an 18-bit transfer and then merge the two reads into an 18-bit value in your own code.

    But I don't understand your question since your sentences doesn't seem to agree with your code. You mentions TI SSI, but then your code contains a comment

    /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
    LPC_SSP1->CR0 = 0x075F;
    

    The assign seems to be a mixture between SPI and TI SSI.

    Next thing here is that you talk about having connected 2 wires between processor and your slave device. For two-way communication you should have 4. But what about your FS signal?

    Another thing is that if not in loopback mode you have two sends but one receive:

    LPC_SSP1->DR = buf; <= send
    while ( (LPC_SSP1->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
    
    LPC_SSP1->DR=0x0000; <= send
    receive[0] = LPC_SSP1->DR; <= receive
    

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