ADUC7020 SPI issue

Hello, I encounter issue using the aduc7020 in spi slave mode.
I am implementing a spi driver in assembler by polling the SPISTA register status and with a clock parity and clockphase set to 1.

I do observe corrupted reading/writing and can t provide a confident result.

Is there any known limitation or bugs on the silicon of this chip?

Thank you

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  • A SPI slave are normally never asynchronous. It needs a clock signal to the SPI logic that controls the internal state machine - among other things how often the signals should be polled.

    This clock frequency must normally be a fixed number of times faster than the clock frequency used on the clock signal of the SPI bus.

    So how fast do you run the SPI bus, and what clock frequency does that ADUC7020 have to run the internal SPI slave state machine?

    Next thing is to make sure both sides agrees on phase and polarity of the clock signal - when they mismatch between master and slave, you get racing conditions where the transmitted signal changes just as the receiver samples the value.

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  • A SPI slave are normally never asynchronous. It needs a clock signal to the SPI logic that controls the internal state machine - among other things how often the signals should be polled.

    This clock frequency must normally be a fixed number of times faster than the clock frequency used on the clock signal of the SPI bus.

    So how fast do you run the SPI bus, and what clock frequency does that ADUC7020 have to run the internal SPI slave state machine?

    Next thing is to make sure both sides agrees on phase and polarity of the clock signal - when they mismatch between master and slave, you get racing conditions where the transmitted signal changes just as the receiver samples the value.

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