Hi, I am trying to communicate SSP on 2 LPC23xx boards. One is Master and other is Slave. Master Board Sending data correctly but Slave Board is not receiving data.
Please help...or send Slave mode code ...initialization of SSP Slave is According to Datasheet.
Thank You
How do you intend to receive the data? Polling or via an interrupt?
Something like this could help you (this code was written for LPC24xx). Note that MISO is _not_ used in this case, as it is not useful to have the master generate clock pules for the slave (in this case):
init:
PINSEL0 |= (2<<12) ; // P0.6 SSEL1 PINSEL0 |= (2<<14) ; // P0.7 SCK1 //PINSEL0 |= (2<<16) ; // P0.8 MISO1 - not used, peers always transmit as a SPI master, see comments of 'spi_send_data' PINSEL0 |= (2<<18) ; // P0.9 MOSI1 // SSP clock prescale register SSP1CPSR = 100 ; // at peripheral clock speed of 16[MHz], a value of 140 yields 12.5[KB]/sec // SSP (SPI) control settings // 8 bit transfers, SPI frame format, CPOL = 1, CPHA = 1, SCR = 1 (bit rate = PCLK/(SSP1CPSR * (SSP_SCR_BIT + 1) ) ) SSP1CR0 |= (7<<SSP_DSS_BIT) | (0<<SSP_FRF_BIT) | (1<<SSP_CPOL_BIT) | (1<<SSP_CPHA_BIT) | (0<<SSP_SCR_BIT) ; #ifdef IO l_master_or_slave = 0 ; // master FIO_PORT_DIR(SPI_MASTER_IO_PORT) |= (1<<SPI_MASTER_IO_PIN) ; // output SPI_IO_MASTER_BIT_RESET // init GPIO 0.SPI_MASTER_DISPLAY_PIN interrupt IO0_INT_EN_F |= (1<<SPI_MASTER_DISPLAY_PIN) ; #elif DISPLAY l_master_or_slave = 1 ; // slave FIO_PORT_DIR(SPI_MASTER_DISPLAY_PORT) |= (1<<SPI_MASTER_DISPLAY_PIN) ; // output SPI_DISPLAY_MASTER_BIT_RESET // init GPIO 0.SPI_MASTER_IO_PIN_INPUT interrupt IO0_INT_EN_F |= (1<<SPI_MASTER_IO_PIN_INPUT) ; #endif // loop back mode disabled, SSP disabled, I/O part master / display part slave, SOD = 0 SSP1CR1 |= (0<<SSP_LBM_BIT) | (0<<SSP_SSE_BIT) | (l_master_or_slave<<SSP_MS_BIT) | (0<<SSP_SOD_BIT) ; // enable interrupts - RORIM, RTIM, RXIM SSP1IMSC |= (1<<SSP_RORIM_BIT) | (1<<SSP_RTIM_BIT) | (1<<SSP_RXIM_BIT) ; // install ISR for SPI traffic install_irq(SSP1_INT, (void *)spi_handler, IRQ_PRIORITY_7) ; // enable SSP1 controller SSP1CR1 |= (1<<SSP_SSE_BIT) ;
IRQ:
__irq void spi_handler(void) { // determine the cause of the interrupt if ( (SSP1MIS>>SSP_RORMIS_BIT) & 1) { // RORMIS bit is 1 if another frame was completely received while the RxFIFO was full SSP1ICR = (1<<SSP_RORIC_BIT) ; } if ( (SSP1MIS>>SSP_RTMIS_BIT) & 1) { // RTMIS bit is 1 if the Rx FIFO is not empty, has not been read for a "timeout period" handle_incoming_spi_data() ; // clear interrupt SSP1ICR = (1<<SSP_RTIC_BIT) ; } if ( (SSP1MIS>>SSP_RXMIS_BIT) & 1) { // interrupt is cleared by reading the FIFO handle_incoming_spi_data() ; } // clear interrupt VICVectAddr = 0 ; }
"Note that MISO is _not_ used in this case, as it is not useful to have the master generate clock pules for the slave (in this case)"
What do you mean by that?
MISO on the slave doesn't have anything to do with need for clock pulses.
The clock signal is always master -> slave.
The MOSI signal is (often) connected master -> slave.
The MISO signal is (often) connected slave -> master.
Some programs are always sending data in both directions concurrently.
Some are sending commands on MOSI while the slave sends zero or one bits. Then the master switches to sending dummy bits (normally zeros or ones) while picking up incomming bits from the slave.
So yes - sometimes MISO isn't used. But irrelevant to the need for clock pulses.
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