external irq called twice depending on optimization level

Controller: STM32F103
Compiler: ARM-MDK 4.14

I have a flow-meter connected to a portpin. I like to count on rising and falling slope. So I initialized this ext. irq to meet these requirements. The software works since a couple of weeks without any problem.

This week I recognized that the optimiziation level is accidentally set to 0. Ok, no problem, I set it to maximum level 3.

After this action the code shrunk significantly - nice!

But my flow-meter gave me values twice as high as usual.

I put some LED-switchings into the isr and could detect that every slope of the flow meter triggers the isr exactly twice.

This is my isr for EXTI Line 14

  void IHW_DfmImpulseIsr(void) {
    COUNT_iCount(COUNT_kDFMBRUEHWASSER);  //count on each slope
    EXTI_ClearITPendingBit(EXTI_Line14);
  } // IHW_DfmImpulseIsr()

I found an other thread, that the reason might be that the isr-pending-bit is not cleared in time. But where is the casual connetion to optimization level.

And the crucial question, HOW to clear pending-bit correctly? Unfortunately I could not find any commendation neither from KEIL/ARM nor from ST.

Parents
  • Clear the interrupt flag as early as possible in your ISR. That way you increase your chance of the interrupt flag actually having been cleared before leaving the ISR. Otherwise you might catch the same interrupt again, which explains the "twice as high" values. To be on the safe side you might also want to consider inserting a synchronization barrier (DSB) before leaving the ISR to ensure that memory accesses are guaranteed to have completed.

    Hope this helps,
    Marcus
    http://www.doulos.com/arm

Reply
  • Clear the interrupt flag as early as possible in your ISR. That way you increase your chance of the interrupt flag actually having been cleared before leaving the ISR. Otherwise you might catch the same interrupt again, which explains the "twice as high" values. To be on the safe side you might also want to consider inserting a synchronization barrier (DSB) before leaving the ISR to ensure that memory accesses are guaranteed to have completed.

    Hope this helps,
    Marcus
    http://www.doulos.com/arm

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