<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>help about opcode</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/26975/help-about-opcode</link><description> 
hello 
i have an opcode of BNE branch which is 1AFFFFF9 and i want to know
to which address go this branch i mean how i know what is the next
address executed 
 </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/156452?ContentTypeID=1</link><pubDate>Tue, 19 Oct 2010 00:01:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2bef7a0a-d4fb-4c4a-8fe4-c4269c27576b</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
thank you very much for your help&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/156263?ContentTypeID=1</link><pubDate>Sun, 17 Oct 2010 10:32:52 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7b40c4e4-e9c0-4a0c-99bd-e6cf41e64a84</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Indeed.&lt;/p&gt;

&lt;p&gt;
But note that the decision to execute or not relies only on the
flags - there is no relation between the instructions themselves.&lt;/p&gt;

&lt;p&gt;
In other words, it doesn&amp;#39;t matter what instruction set the flags;
it&amp;#39;s only the state of the flags that matters.&lt;/p&gt;

&lt;p&gt;
I hope the distinction is not too subtle that it gets lost in
translation...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/156034?ContentTypeID=1</link><pubDate>Sun, 17 Oct 2010 09:51:17 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d89ef2e5-e3f6-469b-b7f9-dc3e0f0a165d</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
A number of processors have support for conditional processing of
instructions. That means that when they reach the instruction (in
this case the second instruction), it checks a processor flag to
decide if it should process the instruction or treat it as a NOP
instruction and continue to the third instruction.&lt;/p&gt;

&lt;p&gt;
The second instruction in this case is only performing a
comparison if the first instruction found a match.&lt;/p&gt;

&lt;p&gt;
The third instruction is also conditional. So it will only perform
an ADD if the previous two instructions both compared equal. So the
add only happens if instr1 arg1 == arg2 and instr2 arg1 == arg2.&lt;/p&gt;

&lt;p&gt;
If instruction 2 sees a difference, then both second and third
instructions will be treated as &amp;quot;NOP&amp;quot; instructions. If first
instruction matches, and second instruction sees a mismatch, then the
third instruction will be treated as a &amp;quot;NOP&amp;quot;.&lt;/p&gt;

&lt;p&gt;
So the only relation involved is that the conditional instructions
will be processed or not, based on the result of previous
instructions.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/155784?ContentTypeID=1</link><pubDate>Sun, 17 Oct 2010 09:09:21 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:dbc6078b-debd-4bab-9e9a-ebbe49540f09</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
What do you mean by &amp;quot;relation&amp;quot; here?&lt;/p&gt;

&lt;p&gt;
As far as the CPU is concerned, it just executes instructions in
order (until changed by some kind of branch or interrupt) - so there
is no &amp;quot;relation&amp;quot; between instructions other than the order in which
they appear in memory.&lt;/p&gt;

&lt;p&gt;
Unless you&amp;#39;re thinking of some other meaning of &amp;quot;relation&amp;quot;
here?&lt;/p&gt;

&lt;p&gt;
The order in which instructions appear in memory is determined by
the programmer as the order needed to achieve the purpose of the
program.&lt;/p&gt;

&lt;p&gt;
In the case of a High-Level Language (HLL), the compiler will
synthesise the high-level operations with an appropriate sequence of
low-level (machine) instructions.&lt;/p&gt;

&lt;p&gt;
Does that answer your question?&lt;br /&gt;
If not, you need to explain the question more clearly...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/155501?ContentTypeID=1</link><pubDate>Sun, 17 Oct 2010 07:53:05 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b54e4319-1f5c-4fd0-9c32-715d64b78279</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
thank you Bradford for your help&lt;/p&gt;

&lt;p&gt;
that&amp;#39;s mean before the execution of The second instructon it must
check the first instruction CMP r0,r1 (instruction set).&lt;/p&gt;

&lt;p&gt;
but up till now i don&amp;#39;t understand the relation between the first
and the second instruction can you give me an example&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/155139?ContentTypeID=1</link><pubDate>Sat, 16 Oct 2010 17:16:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b90a00cd-b3d6-454b-ba3e-b6dfd75e9e15</guid><dc:creator>doubt that my ISP Al Bradford</dc:creator><description>&lt;p&gt;&lt;p&gt;
insructions--insructions-- instructions.&lt;br /&gt;
Wish I could type.&lt;br /&gt;
Bradford&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/154717?ContentTypeID=1</link><pubDate>Sat, 16 Oct 2010 17:14:27 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a2d9f32d-5d6a-42ff-b9dd-58b734588ed4</guid><dc:creator>doubt that my ISP Al Bradford</dc:creator><description>&lt;p&gt;&lt;p&gt;
You really need to look a the instruction set a little more.&lt;br /&gt;
Where is the EQ status bit set?&lt;br /&gt;
The second line says compare R2,R3 AND the EQ status bit.&lt;br /&gt;
The same with the third line. Add only if the EQ bit is 1.&lt;br /&gt;
Remember, almost all insructions in the ARM can be conditional.&lt;br /&gt;
Bradford&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/154205?ContentTypeID=1</link><pubDate>Sat, 16 Oct 2010 15:09:30 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e8cada0c-2931-4007-ae6a-56ed07908780</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
i want to ask you andy&lt;br /&gt;
look at this assembly code&lt;/p&gt;

&lt;p&gt;
IF (a == b) AND (c == d)&lt;br /&gt;
THEN e = e + 1;&lt;br /&gt;
-------------&lt;br /&gt;
CMP r0,r1 Compare a and b&lt;br /&gt;
CMPEQ r2,r3 If a == b THEN compare c and d&lt;br /&gt;
ADDEQ r4,r4,#1 if c == d then increment e by 1&lt;/p&gt;

&lt;p&gt;
The next instruction, CMPEQ r2,r3,performs a comparison only if
the result of the first line was true how the processor linked the
first and the second and the third instruction with each other!&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/153607?ContentTypeID=1</link><pubDate>Sat, 16 Oct 2010 13:10:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b1e580c4-c8d3-4e19-b0df-f75ff545f8f3</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
do you mean how reach to the target address it is my quetion an i
get the answer in the forum which you refer to it&lt;/p&gt;

&lt;p&gt;
Target Address = PC + 8 words(offset)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/152923?ContentTypeID=1</link><pubDate>Sat, 16 Oct 2010 00:45:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:db6502a8-c87c-4b7f-aba9-cc06923e313f</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;a href="http://www.keil.com/support/man/docs/armasm/armasm_Cacdbfji.htm"&gt;http://www.keil.com/support/man/docs/armasm/armasm_Cacdbfji.htm&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/152138?ContentTypeID=1</link><pubDate>Fri, 15 Oct 2010 15:38:42 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ad4bae9a-f241-4a94-91e2-7b043a62f5b9</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
You want to know what address the jump will jump to, don&amp;#39;t
you?&lt;/p&gt;

&lt;p&gt;
You have found that the FFFFF9 is an &lt;i&gt;offset&lt;/i&gt;.&lt;/p&gt;

&lt;p&gt;
You know that an &lt;i&gt;offset&lt;/i&gt; is applied to some &amp;quot;base&amp;quot; address
to give a resulting address - how do you think that would be applied
in the case of this branch instruction...?&lt;/p&gt;

&lt;p&gt;
It&amp;#39;s time for you to do some thinking, rather than just wait for
answers to be handed to you on a plate.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/151394?ContentTypeID=1</link><pubDate>Fri, 15 Oct 2010 13:34:15 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2e812b0f-6956-45b6-a63c-a28e585579b6</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
i didn&amp;#39;t understant your quetions well&lt;/p&gt;

&lt;p&gt;
let&amp;#39;s take the branch BNE ,its opcode is 1AFFFFF9&lt;br /&gt;
1 = Condition: not equal&lt;br /&gt;
A = Branch (Link = 0 if =1 the curent address it will save in
R14)&lt;br /&gt;
offset = FFFFF9&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/150770?ContentTypeID=1</link><pubDate>Thu, 14 Oct 2010 23:32:24 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:88bc7410-96f5-4644-b7f6-58b518aec380</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Correct.&lt;/p&gt;

&lt;p&gt;
So how do you think that is applied in the case of a jump
instruction?&lt;/p&gt;

&lt;p&gt;
What do you think is considered the &amp;quot;base&amp;quot; address in this
context?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/144972?ContentTypeID=1</link><pubDate>Thu, 14 Oct 2010 16:57:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:63966ade-9d11-45de-8ccc-7bda0724aee1</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
the offset is an optional number which is added to the address
base(address of memory location) for jump or go to a desired
address.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/142727?ContentTypeID=1</link><pubDate>Thu, 14 Oct 2010 11:32:52 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:4219ee26-9adc-46f8-9b94-ca1224233e03</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
OK, so you found some pages that &lt;i&gt;mention&lt;/i&gt; &amp;quot;Offset&amp;quot;.&lt;/p&gt;

&lt;p&gt;
But do &lt;i&gt;&lt;b&gt;you&lt;/b&gt;&lt;/i&gt; actually understand what &amp;quot;offset&amp;quot;
&lt;b&gt;means&lt;/b&gt;?&lt;/p&gt;

&lt;p&gt;
BTW: those pages are using it in the specific context of the intel
x86 - which is not relevant here...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/139721?ContentTypeID=1</link><pubDate>Thu, 14 Oct 2010 05:13:34 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:39c7e2f7-ba03-4616-a2c2-8497e7c7f890</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
i didn&amp;#39;t ignore any person if you think so i&amp;#39;m sorry Andy i asked
in several forum maybe i find a good and easy explaination only.&lt;/p&gt;

&lt;p&gt;
about your quetion&lt;br /&gt;
&lt;a href="http://mirror.href.com/thestarman/asm/debug/Segments.html"&gt;mirror.href.com/.../Segments.html&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;

&lt;a href="http://cmagical.blogspot.com/2009/11/memory-cell-residence-memory.html"&gt;cmagical.blogspot.com/.../memory-cell-residence-memory.html&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/136300?ContentTypeID=1</link><pubDate>Wed, 13 Oct 2010 16:14:31 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:256db63b-1e50-4364-92ca-92be2d168aaf</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
You already have a perfectly good answer!&lt;/p&gt;

&lt;p&gt;
If you want a better answer, you need to provide a better question
which clearly explains what, exactly, you want to know and why,
exactly, you can&amp;#39;t understand the other answer.&lt;/p&gt;

&lt;p&gt;
Simply ignoring people who have taken time to answer your question
is not a great way to endear others to help you...&lt;/p&gt;

&lt;p&gt;
Do you understand what an &amp;quot;&lt;b&gt;Offset&lt;/b&gt;&amp;quot; means?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/126449?ContentTypeID=1</link><pubDate>Wed, 13 Oct 2010 14:16:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8bfc1480-1f48-401c-bafd-91c812efd739</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
yes i asked there but up till now i didn&amp;#39;t know how can i
determine the jump address and i ask here maybe i find a better
answer&lt;/p&gt;

&lt;p&gt;
take a look at this code&lt;/p&gt;

&lt;p&gt;
000138: e92d40f0 stmdb sp!, {r4, r5, r6, r7, lr}&lt;br /&gt;
00013c: e1a07000 mov r7, r0&lt;br /&gt;
000140: e59f00bc ldr r0, [pc, #188] ; [000204]&lt;br /&gt;
000144: e1a06001 mov r6, r1&lt;br /&gt;
000148: e59f10b8 ldr r1, [pc, #184] ; [000208] &amp;quot;w&amp;quot;&lt;br /&gt;
00014c: eb00033e bl 000e4c(33e)&lt;br /&gt;
000150: e2505000 subs r5, r0, #0 ; 0x0&lt;br /&gt;
000154: 0a000027 beq 0001f8(27) ; jump&lt;/p&gt;

&lt;p&gt;
000158: e3560064 cmp r6, #100 ; 0x64 &amp;#39;d&amp;#39;&lt;br /&gt;
00015c: 1a000008 bne 000184(8) ; jump&lt;br /&gt;
000160: e59f40a4 ldr r4, [pc, #164]&lt;br /&gt;
000164: e1a00004 mov r0, r4&lt;br /&gt;
000168: eb000544 bl 001680(544)&lt;br /&gt;
00016c: e1a02000 mov r2, r0&lt;br /&gt;
000170: e1a00004 mov r0, r4&lt;br /&gt;
000174: e3a01001 mov r1, #1 ; 0x1&lt;br /&gt;
000178: e1a03005 mov r3, r5&lt;br /&gt;
00017c: eb000339 bl 000e68(339)&lt;br /&gt;
000180: ea000007 b 0001a4(7) ; jump&lt;/p&gt;

&lt;p&gt;
000184: e59f4084 ldr r4, [pc, #132] ; [000210]&lt;/p&gt;

&lt;p&gt;
look at this bne opcode&lt;br /&gt;
00015c: 1a000008 bne 000184(8) ; jump&lt;br /&gt;
how they determine the jump address 000184&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/116061?ContentTypeID=1</link><pubDate>Wed, 13 Oct 2010 07:28:27 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b02af92c-8c0d-44ba-8336-ff34cd41edf0</guid><dc:creator>Marcus Harnisch</dc:creator><description>&lt;p&gt;&lt;p&gt;
You had asked the same question in another forum and received an
appropriate answer here &lt;a href="http://embdev.net/topic/193406#1892567"&gt;embdev.net/.../193406&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
--&lt;br /&gt;
Marcus&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/102301?ContentTypeID=1</link><pubDate>Wed, 13 Oct 2010 05:25:59 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:453e743f-6fc1-4064-95ee-cb56e2527855</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
thank you Andy for your reply&lt;br /&gt;
i know that this branch instruction jump to an address but how can i
determine the jump address&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/90668?ContentTypeID=1</link><pubDate>Mon, 11 Oct 2010 14:29:14 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:64429912-5417-4e40-baf2-cd5e0847def9</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;a href="http://infocentre.arm.com"&gt;http://infocentre.arm.com&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: help about opcode</title><link>https://community.arm.com/thread/58754?ContentTypeID=1</link><pubDate>Mon, 11 Oct 2010 13:09:30 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c302e9fb-cb13-4440-9ae0-d4c15b2f1e1c</guid><dc:creator>sa ha</dc:creator><description>&lt;p&gt;&lt;p&gt;
the processor is ARM7TDMI&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>