It's time to do some work on you're compiler. It generates the same code it did 20 years ago. I have to do tricks, instead of writing normal portable code, to get it to generate good code or just use inline assembler. This of course is nothing new, I've been telling you this for almost a decade. Keep in mind that all Intel processors are little endian and that you're compiler generates big endian code, why? You should at least offer a compiler switch to select endianness. Why don't you support C++ and MISRA? Oh and BTW IAR does all of the above TODAY! So clearly they haven't been standing still. (Notice who wrote the paper.)
www.eetimes.com/.../The-Inefficiency-of-C--Fact-or-Fiction-
Byte suddenly being little or big-endian? Impossible.
The bits in a byte are just that - bits. Don't spend too much time figuring out the bit addressing, thinking that would have anything to do with the little/big endian issue.
Almost all processors defines bytes/words/... to have bit 0 as least significant bit. Creating a bit-addressing instruction, it would be very stupid to suddenly number the bits: 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 ... just to make a statement about big/little order.
But if you do want to have fun - look at some Freescale processors where the bits are numbered in reverse order. Truly magnificent to read a schematic and figure out that A30 is not a really "big" address line but one of the smallest. These bit issues probably resulted from some people stupidly trying to extrapolate word endianness into the naming of individual bits too.
I don't think I have ever seen a little-endian processor numbering bit 0 as the most significant bit. But big-endian processors sometimes names the most significant bit 0, and sometimes the least significant bit.
Hence, even if you do try to use the bit endianness in the discussion, the use of bit0 as least significant can't be used as any proof since it is used by bost little-endian and big-endian processors.
Next thing. If you have a 3-byte instruction, one byte op-code and two byte address, you shouldn't try to merge the opcode with the first byte of the address and imply big or little endian. That is just an ugly extrapolation.
"Having to byte swap because of a lack of compiler switch means extra code space, slower execution and ..."
That depends entirely on the optimization capabilities of the compiler.
Do you really remember the level of optimization of the first Keil C compiler? I do; it was close to zero and very likely to produce faulty code. Compare that with the current release.
And you said at the very start:
"It generates the same code it did 20 years ago."
That is so not the case. I still have a copy of 3.05 (circa 1990) if anyone wants to see a comparison of produced code, but have long since thrown out all my copies if error reports I sent to Keil.
"... and is a maintenance issue."
Surely someone who writes portable code should be capable of looking after such issues as a matter of course.
If you're going to come out with such confrontational statements then you really should make sure you are factually correct.
It's really a matter of convenience and cost. Having to byte swap because of a lack of compiler switch means extra code space, slower execution and is a maintenance issue.
"That's a burry your head in the sand answer."
Not at all. I've faced similar(ish) situations in the past (but stress not concerning Keil) and I always have the ultmiate choice; i.e., find another employer.
If your opinion is that the endian-ness is so critical in the 8051 architecture, then it suggests to me that you've gained little real experience in your 25+ years.
It is up to the developer to fully understand the tools, how they are used and (very importantly) how to use them effectively. If you can't effectively work around such a limitation then it says far more about your abilities that it does the Keil compiler.
... there is no such thing as portable code
I wouldn't be fond of that idea but I use the same code on an 8051 and on Windows.
The real answer is simple. YOU have a choice. If YOU don't like it, then YOU don't need to use it.
That's a burry your head in the sand answer. Not everyone does. Some the decision is made for them before they even work for their company. Others are limited by budgets. And still others have to use the tools that the chip manufacture has partnered with.
My point is why pay for maintance
Oh, for Pete's sake. So don't pay and do us all a favour and get lost, why don't you?
Is this forum only read by people that work for the company and are set in their ways against listening to customers?
You really need to get help. Your paranoia is getting way out of hand.
If you want optimum code out of Keil you don't have a choice but to deal with DPTR.
I asked for a demonstration of necessity of two things, and you answer with a vague claim regarding only one of them. why even bother? Is it really that hard to just admit that you're wrong?
I'll repeat: DPTR is not little-endian in any meaningful way. There's nothing you can do with DPH and DPL that would change in any way if their locations were exchanged --- or, for that matter, if they were moved to completely random locations each.
"Kiel is the only one that I know of ..."
"I will not thank Kiel or Arm for contining ..."
Looks like you get more than just a little bit confused when it comes to details.
"Is this forum only read by people that work for the company and are set in their ways against listening to customers?"
No.
Personally I like the product and find it far better than the we attempt do it all attitude of the competition.
If you want optimum code out of Keil you don't have a choice but to deal with DPTR. That is my point as to the fact that in 20 years they haven't worked on the compiler. I have compared the output of code from the 80's and now and it's the same. As for DPL and DPH, when writing tight code it can save you code space and clocks to load one of them directly instead of DPTR.
While the article uses IAR's ARM C/C++ complier as an example it is a general purpose article that points out that C++ has great benefits over C and when used appropriately adds no overhead.
I've found the 8051 C friendly, not quite to the level of the pdp like it was originally intended but good enough with some minor language extensions.
Kiel is the only one that I know of that seperates C from C++ at this point.
My point is why pay for maintance if they don't do that? The business case is that people are paying for bug fixes and new features and since the 8051 is the most used processor on the planet every year it has quite the customer base. I will not thank Kiel or Arm for contining with a product that brings money in every year which they do not provide support like other vendors do. This complier is not chiseled in stone, if they want they can add features to it as I've pointed out.
I just came back from a show where the Keil people requested that I post this to their forums because they wanted their management to read what their customers want and what their compeditors offer (it always has more weight from the outside than within).
Not Feeling like Registering Right Now. But the article is for ARM not 8052. The 8052 is Hostile to C let alone C++. It has been talked about for years, does IAR have a one? Ceibo had one years back, those that used it said it was more a science project. Not a lot of room for the actual program.
Remember that C and C++ have diverged. There are some subtle differences that have crept in over the years. There is not C/C++ anymore.
As far as endianess like may other things the decision was made long ago and for good or bad it is not changing now. Maybe the origional programmer was a Motorola guy. Or the code they started with was that way. Maybe it made the compiler code easier. But, now it is what it is. And I do not think the business case would say investing in a big / little option would have a big return on investment. Be thankful that ARM still supports the compiler and did not end of life it. Or thank Keil for making them keep it going.
Well Intel disagrees with you and their opinion is the only one that really matters.
Care giving a citation of an actual statement by Intel, about the MCS51 architecture, that backs up your claim?
All the registers are little endian
Nonsense. The vast majority of 8051 registers are single bytes. Endianness can't even be defined for those. So much for "all registers".
capture 2
No such thing on an actual 8051.
timer/counter 0-2
Care explaining how a 16-bit timer stored in SFR addresses 8A and 8C (with a rather unrelated other SFR in between, at 8B) is little endian in any "CRITICAL" way?
Oh, and there's no such thing as timer/counter 2 in an actual 8051.
just read the data books
Which of the roughly 500 different data books describing 8051 variants in particular?
Oh, right, you wont't/can't divulge the particulars. Sure. And just because you're paranoid doesn't mean THEY are NOT out to get you.
forces little endian alignment
Nobody can force that, because that's a meaningless combination of words.
So do you work for Keil and are the person that got it backwards in the first place and are now trying to defend that mistake?
A couple posts before you were trying to discredit me as being too young to know what big-/little endian is about, and now I'm supposed to be none less than the Evil Mastermind that ruined your world? Could you make up your mind?
Did it ever occur to you that if all the world disagrees with you, this might be because you're plain and simply wrong?
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