Hi there, I have problems setting up the two CAN ports on the MCBSTM32C demo board. I got them to work in loopback mode but in normal mode the INAK bit doesn't set itself to 0.
In the manual it says that the hardware has to monitor 11 consecutive recessive bits to initialise. How to you sent the bits to the port if none of the CAN ports are working? Do I have to set up CAN1 in loopback mode, send 11 bits to CAN2, switch CAN1 to normal mode and then use CAN2 to send 11 bits to CAN1?
The other possibility might be that I didn't set up the CAN ports correctly. Has anybody got an example how to set up the clocks and all the other registers to make CAN1 and CAN2 work?
Thanks, Karsten
But what have you electrically connected? How do you make sure that the bus is in recessive mode?
You are aware of the meaning of recessive and dominant bits?
See this link: en.wikipedia.org/.../Controller_area_network
So correctly connected, you don't need to "send" any 11 recessive bits.
Hi Per, Thanks for your reply.
I only connected CAN1 of the demo board to CAN2 with a 60 Ohm resistor between the CAN+ and CAN- pins. I want to send messages between CAN1 and CAN2 for testing purposes.
As far as I understand it a recessive bit is when there is no voltage across the CAN+ and CAN-pins.
I'm assuming the 11 consecutive recessive bits have to be flanked by dominant bits. Otherwise not sending anything would be sufficient to synchronise the CAN port. If my assumption is correct the CAN port would have to receive a base frame with an identifier of 0x7FF and a dominant RTR bit. One of the nodes on the bus would have to send such a frame. Is this correct?
In this particular case this would be possible via the loopback mode. Later on I would like to read data from a CANopen position encoder attached to only one of the ports. In this case the encoder would have to send such a frame until communication has been established. I'm not sure yet if CANopen sends such a sync frame at power up by default.
I'm assuming the 11 consecutive recessive bits have to be flanked by dominant bits.
Why?
Otherwise not sending anything would be sufficient to synchronise the CAN port.
What do you assume it would have to synchronize with?
Is this correct?
No.
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