Has anyone used the __pld() instruction intrinsic with the Keil compiler tools?
According to the ARM V7-M Architecture Reference Manual: "The effect of these memory system hints is IMPLEMENTATION DEFINED".
Please. No 'what are you using this for' questions. Right now this is just a research on my part to determine whether or not I would need to use this intrinsic. Since this is implementation defined I would need to know if this is even used within the Keil environment and what would be the benefit (if any) over using this rather than say optimization level 3 or even using the volatile keyword.
Thanks.
You should probably read the relevant compiler reference manual section as well: www.keil.com/.../armccref_cjagadac.htm
Since this is implementation defined I would need to know if this is even used within the Keil environment
If you use it explicitly, it will be used. I doubt the compiler emits such an instruction, though.
and what would be the benefit (if any) over using this rather than say optimization level 3 or even using the volatile keyword.
Some processors are equipped with data caches and prefetch units. If you are working with one of those, this intrinsic might help you optimize memory reads in your program. This will probably be completely opaque to the compiler, so no intersection with optimization level or use of volatile.
Thanks Mike.
According to your link: "This intrinsic inserts a data prefetch...".
Yet the ARM manual states: "Memory hints allow you to provide advance information to memory systems about future memory accesses, without actually loading or storing any data."
So the Keil compiler actually executes a prefetch (actually loads or stores) the data when __pld() is used?
Not having used this feature, I cannot say anything about it. But I am curious though: will you share with us the circumstances where this might be beneficial for you? I'm just asking out of curiosity!
From the ARM manual:
"For example: In systems with a DMA that reads memory locations that are held in the data cache of a processor, a breakdown of coherency occurs when the processor has written new data in the data cache, but the DMA reads the old data held in memory. In a Harvard architecture of caches, a breakdown of coherency occurs when new instruction data has been written into the data cache and/or to memory, but the instruction cache still contains the old instruction data."
Just trying to understand myself.
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