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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/26246/cortexm0-multiple-svchandlers</link><description> 
Hi 
Is there some example how i can create multiple sodtware interrupts
through the SVC_Handler ? 

 
For now i am only able to call one software interrupt. 

 
The code (swi.s) i used for the lpc21xx does not work on the
lpc1111 

 
Is there some code</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/139752?ContentTypeID=1</link><pubDate>Wed, 17 Nov 2010 15:11:09 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5c1cb9aa-ba93-46fb-9227-7cb39db3835d</guid><dc:creator>Johan Sagaert</dc:creator><description>&lt;p&gt;&lt;p&gt;
Are there no unwanted side effects when disabling interrupts from
within an isr ?&lt;/p&gt;

&lt;p&gt;
I am not 100% sure, but in my &amp;#39;8051&amp;#39; period, turning off irqs
could lead to missed irq&amp;#39;s.&lt;/p&gt;

&lt;p&gt;
Johan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/136322?ContentTypeID=1</link><pubDate>Mon, 08 Nov 2010 02:12:14 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:51ac9afe-80d6-45fb-a0bd-2a19a35864b6</guid><dc:creator>Per Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
It is quite easy to believe that if you turn off interrupts, your
processor will not detect interrupts. It still does.&lt;/p&gt;

&lt;p&gt;
Next thing that is easy to believe is that if you turn off
interrupts, you get more latencies and jitter. But when you play with
your SWI(0) handler, you set the processor in a mode that has higher
priority than your normal interrupts. So they will be just as
disabled as if you had turned off interrupts the direct way.&lt;/p&gt;

&lt;p&gt;
So in the end, you have two similar ways to block interrupts while
you perform your critical section.&lt;/p&gt;

&lt;p&gt;
So make sure you know the reasons for doing it one thing instead
of some other way.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/126492?ContentTypeID=1</link><pubDate>Mon, 08 Nov 2010 01:51:32 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:995a3cbd-19be-4ea0-83de-e7ed36605e15</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
But &lt;i&gt;&lt;b&gt;why&lt;/b&gt;&lt;/i&gt; not?&lt;/p&gt;

&lt;p&gt;
Of course, you may have a (very) good reason - in which case, you
should be able to explain it.&lt;/p&gt;

&lt;p&gt;
Without knowing &lt;i&gt;&lt;b&gt;why&lt;/b&gt;&lt;/i&gt; you&amp;#39;re doing something, it is
impossible for people to know whether or not suggestions are
appropriate to your situation.&lt;/p&gt;

&lt;p&gt;
And it might be that you really don&amp;#39;t need to do it this way - and
there are (much) better ways to do it...&lt;/p&gt;

&lt;p&gt;
Remember: nobody knows anything about you or your project &lt;i&gt;other
than&lt;/i&gt; what you explicitly state in your posts!&lt;/p&gt;

&lt;p&gt;
Also, please note the instructions on how to post source code:&lt;/p&gt;

&lt;p&gt;
&lt;a href="http://www.danlhenry.com/caps/keil_code.png"&gt;www.danlhenry.com/.../keil_code.png&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/126493?ContentTypeID=1</link><pubDate>Mon, 08 Nov 2010 01:47:38 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:aaedd986-b760-48d6-95f9-aee50c59d401</guid><dc:creator>Marcus Harnisch</dc:creator><description>&lt;p&gt;&lt;p&gt;
&amp;gt; I dont want to disable the interrupts, here is how it worked
on lpc 21xx&lt;/p&gt;

&lt;p&gt;
Sure, but why not? The effect of using an SVC (formerly known as
SWI) to prevent interrupts from becoming active is no different from
disabling them. In fact, the latter is a lot easier to program and
likely more efficient (both, size and performance).&lt;/p&gt;

&lt;p&gt;
Regards&lt;br /&gt;
Marcus&lt;br /&gt;
&lt;a href="http://www.doulos.com/arm/"&gt;http://www.doulos.com/arm/&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
PS: Please use proper tags if you post code&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/116116?ContentTypeID=1</link><pubDate>Mon, 08 Nov 2010 01:30:56 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c30825cd-efaf-41b0-b769-bc26964703cf</guid><dc:creator>Johan Sagaert</dc:creator><description>&lt;p&gt;&lt;p&gt;
hi&lt;br /&gt;
I dont want to disable the interrupts, here is how it worked on lpc
21xx&lt;br /&gt;
in my main i simmply called swi_kick_wd ();&lt;br /&gt;
The problem is that the assembly code part from lpc21xx does not work
for the cortex M0 and i don&amp;#39;t know how to change the assemby languase
to make it work.&lt;br /&gt;
The SCC call makes it possible to onse 256 different software
interrupt handlers.&lt;/p&gt;

&lt;p&gt;
///////////// C code part&lt;br /&gt;
/* * Software Interrupt Function accept parameters and run in *
Supervisor Mode (Interrupt protected) */&lt;/p&gt;

&lt;p&gt;
void __swi(0) swi_kick_wd (void);&lt;br /&gt;
void __SWI_0 (void)&lt;br /&gt;
{ WDFEED=0xaa; WDFEED=0x55;&lt;br /&gt;
}&lt;/p&gt;

&lt;p&gt;
void __swi(1) set_io0(unsigned int mask,unsigned int data);&lt;br /&gt;
void __SWI_1 (unsigned int mask,unsigned int pindata)&lt;br /&gt;
{ FIOMASK=mask; FIOPIN=pindata;&lt;br /&gt;
}&lt;/p&gt;

&lt;p&gt;
unsigned int __swi(2) get_io0(unsigned int mask);&lt;br /&gt;
unsigned int __SWI_2 (unsigned int mask)&lt;br /&gt;
{ FIOMASK=mask; return FIOPIN;&lt;br /&gt;
}&lt;/p&gt;

&lt;p&gt;
void __swi(3)setbuzzer(int state);&lt;br /&gt;
void __SWI_3 ( int var)&lt;br /&gt;
{ if (var) { FIO0MASK3=0xfd; FIO0PIN3 =0x02; } else { FIO0MASK3=0xfd;
FIO0PIN3 =0x00; }&lt;br /&gt;
}&lt;/p&gt;

&lt;p&gt;
//assembly code part :&lt;/p&gt;

&lt;p&gt;

;/*****************************************************************************/&lt;br /&gt;

;/* SWI.S: SWI Handler */&lt;br /&gt;
;/*****************************************************************************/&lt;br /&gt;

;/* This file is part of the uVision/ARM development tools. */&lt;br /&gt;
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved.
*/&lt;br /&gt;
;/* This software may only be used under the terms of a valid,
current, */&lt;br /&gt;
;/* end user licence from KEIL for a compatible version of KEIL
software */&lt;br /&gt;
;/* development tools. Nothing else gives you the right to use this
software. */&lt;br /&gt;
;/*****************************************************************************/&lt;/p&gt;

&lt;p&gt;
T_Bit EQU 0x20&lt;/p&gt;

&lt;p&gt;
PRESERVE8 ; 8-Byte aligned Stack AREA SWI_Area, CODE, READONLY
ARM&lt;/p&gt;

&lt;p&gt;
EXPORT SWI_Handler&lt;br /&gt;
SWI_Handler&lt;/p&gt;

&lt;p&gt;
STMFD SP!, {R12, LR} ; Store R12, LR MRS R12, SPSR ; Get SPSR
STMFD SP!, {R8, R12} ; Store R8, SPSR TST R12, #T_Bit ; Check Thumb
Bit LDRNEH R12, [LR,#-2] ; Thumb: Load Halfword BICNE R12, R12,
#0xFF00 ; Extract SWI Number LDREQ R12, [LR,#-4] ; ARM: Load Word
BICEQ R12, R12, #0xFF000000 ; Extract SWI Number&lt;/p&gt;

&lt;p&gt;
LDR R8, SWI_Count CMP R12, R8 BHS SWI_Dead ; Overflow ADR R8,
SWI_Table LDR R12, [R8,R12,LSL #2] ; Load SWI Function Address MOV
LR, PC ; Return Address BX R12 ; Call SWI Function&lt;/p&gt;

&lt;p&gt;
LDMFD SP!, {R8, R12} ; Load R8, SPSR MSR SPSR_cxsf, R12 ; Set SPSR
LDMFD SP!, {R12, PC}^ ; Restore R12 and Return&lt;/p&gt;

&lt;p&gt;
SWI_Dead B SWI_Dead ; None Existing SWI&lt;/p&gt;

&lt;p&gt;
SWI_Cnt EQU (SWI_End-SWI_Table)/4&lt;br /&gt;
SWI_Count DCD SWI_Cnt&lt;/p&gt;

&lt;p&gt;
IMPORT __SWI_0 IMPORT __SWI_1 IMPORT __SWI_2 IMPORT __SWI_3&lt;br /&gt;
SWI_Table DCD __SWI_0 ; SWI 0 Function Entry DCD __SWI_1 ; SWI 1
Function Entry DCD __SWI_2 ; SWI 2 Function Entry DCD __SWI_3 ; SWI 3
Function Entry&lt;br /&gt;
; ...&lt;br /&gt;
SWI_End&lt;/p&gt;

&lt;p&gt;
END&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/104379?ContentTypeID=1</link><pubDate>Mon, 08 Nov 2010 00:16:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:37d7d6c1-a5c0-42fb-8787-1837f49f70b1</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;&amp;quot;What if then just on that moment another IRQ arrives
?&amp;quot;&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
Sorry - I don&amp;#39;t get you?&lt;/p&gt;

&lt;p&gt;
You disable interrupts &lt;b&gt;&lt;i&gt;immediately&lt;/i&gt; before&lt;/b&gt; your
critical code starts; so, when your critical code is running,
interrutps are disabled - therefore, your code cannot be
interrupted!&lt;/p&gt;

&lt;p&gt;
QEF?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/78781?ContentTypeID=1</link><pubDate>Sun, 07 Nov 2010 16:12:20 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:64f07df9-3658-4586-9a2b-5f964c2a23b0</guid><dc:creator>Johan Sagaert</dc:creator><description>&lt;p&gt;&lt;p&gt;
What if then just on that moment another IRQ arravices ?&lt;/p&gt;

&lt;p&gt;
I am not familiar with ASM ASM code&lt;/p&gt;

&lt;p&gt;
In the SVC_handler i should setup a table with vectors for my soft
irq routines&lt;br /&gt;
the requested handler to executes index is in one of the registers.
thats al i could figure out.&lt;/p&gt;

&lt;p&gt;
but i dont know how to do this in assembler&lt;br /&gt;
must be a relative jump in this table.&lt;/p&gt;

&lt;p&gt;
it must be similar like the swi.s from the lpc21xx ARM7 , nut this
is cortex M0 and seems be somewhat different.&lt;/p&gt;

&lt;p&gt;
Johan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CortexM0  Multiple SvcHandlers</title><link>https://community.arm.com/thread/66007?ContentTypeID=1</link><pubDate>Sun, 07 Nov 2010 12:33:39 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:eed69253-c453-4ef1-a5c1-432db1f96144</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Why not just disable interrupts around that code?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>