<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/25707/how-to-enable-i-cache-and-d-cache-on-lpc313x</link><description> 
Hi, 

 
I wish to improve performances of my application by enabling I and
D cache in my LPC3131 chip. 

 
I don&amp;#39;t use any external memories and no OS. 

 
One says me : &amp;quot;The default MMU tables in BootROM map ISRAM area
0x11028000 as non-cacheable areas</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/146444?ContentTypeID=1</link><pubDate>Wed, 23 Sep 2009 03:29:09 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ba78ca9e-c826-4e19-9080-9d450af03b6e</guid><dc:creator>while ();</dc:creator><description>&lt;p&gt;&lt;p&gt;
I take the previous statement back, you should really benefit from
using I-cache because of what you have written.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/144724?ContentTypeID=1</link><pubDate>Wed, 23 Sep 2009 02:41:52 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5860e2a7-f73e-4f29-92a4-361aad77d1a2</guid><dc:creator>bbad </dc:creator><description>&lt;p&gt;&lt;p&gt;
Why do you think so ?&lt;br /&gt;
Don&amp;#39;t you agree that CPU instruction fetch generates activity on the
AHB matrix that should slow down my parallel DMA and USB transfers
?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/142427?ContentTypeID=1</link><pubDate>Wed, 23 Sep 2009 02:23:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:05f1c5cc-89c8-454a-a4ab-d837a0f836da</guid><dc:creator>while ();</dc:creator><description>&lt;p&gt;&lt;p&gt;
I don&amp;#39;t think I cache would provide better performance in your
case.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/139326?ContentTypeID=1</link><pubDate>Wed, 23 Sep 2009 00:59:03 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:da175ef0-08a0-497f-bde2-3edae4de2f9e</guid><dc:creator>bbad </dc:creator><description>&lt;p&gt;&lt;p&gt;
In fact I want to perform parallel transfer :&lt;br /&gt;
- I want to copy data from USB to IRAM1 using USB AHB master&lt;br /&gt;
- And in the same time to copy data from IRAM2 to MCI port using DMA
controller&lt;/p&gt;

&lt;p&gt;
Each transfer taken appart offers good performances, but when I
put them together performances are very low.&lt;/p&gt;

&lt;p&gt;
Therefore I wish to minimize data transfer over AHB matrix mainly
for instruction fetch that generates activity on IRAM1. That&amp;#39;s why I
think I-cache may increase performances of my application.&lt;/p&gt;

&lt;p&gt;
Best regard&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/135917?ContentTypeID=1</link><pubDate>Tue, 22 Sep 2009 10:43:41 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:eb32d94b-7429-487e-950e-3bd4669abddd</guid><dc:creator>while ();</dc:creator><description>&lt;p&gt;&lt;p&gt;
I do not think that there is a point in using caching for internal
RAM as this is usually zero cycle RAM and caching makes no sense
here.&lt;br /&gt;
So caching makes sense for flash or SDRAM and I do not see a point in
your using cache for internal RAM.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/125719?ContentTypeID=1</link><pubDate>Tue, 22 Sep 2009 10:19:23 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:970eb9a5-ebd0-4f6f-ad4f-28210b2a0d30</guid><dc:creator>bbad </dc:creator><description>&lt;p&gt;&lt;p&gt;
Thank you all for help.&lt;/p&gt;

&lt;p&gt;
In fact the blinky example do not use I-Cache when running in
internal RAM. By reading carefully the lpc3131 user manual one can
read the following (Table 74. MMU translation table) :&lt;/p&gt;

&lt;p&gt;
PhyAdd 0x11000000 maps VirtAdd at 0x11000000 with cache disabled
and write buffer disabled&lt;/p&gt;

&lt;p&gt;
But :&lt;/p&gt;

&lt;p&gt;
PhyAdd 0x11100000 maps VirtAdd at 0x11000000 with cache enabled
and write buffer enabled&lt;/p&gt;

&lt;p&gt;
That means that the IRAM is mapped twice in the default MMU
translation table, uncached at PhyAdd 0x11000000, and cached at
0x11100000. And in my system I only use internal RAM.&lt;/p&gt;

&lt;p&gt;
So to use caches, code must be mapped above 0x11100000.&lt;/p&gt;

&lt;p&gt;
Therefore I start to map my code in this way. However I need some
help. I explain next what I have done :&lt;br /&gt;
- I change the .ini script to start code at 0x11129000&lt;br /&gt;
- I change the ldscript to load code at 0x11129000&lt;br /&gt;
- I change the ISRAM_ESRAMX_BASE to 0x111xxxxx in the file
lpc313x_chip.h&lt;br /&gt;
- I change the END_OF_IRAM value to 0x11158000 in the startup
assembly code&lt;br /&gt;
- I force &amp;Acirc;&amp;micro;Vision to believe that LPC3131 RAM is located
above 0x11100000 by modifying the .uv2 file ( Cpu
(IRAM(0x11128000-0x1113FFFF) IRAM2(0x11140000-0x11157FFF) ....)&lt;br /&gt;
- I enable only the I-cache in the startup assembly code&lt;/p&gt;

&lt;p&gt;
Doing this my program seems to start using debugger, but it
crashes quickly. I have a &amp;quot;printf&amp;quot; at the beginning of my code, when
I do step by step debugging the printf is executed but nothing goes
out from UART.&lt;br /&gt;
I try to do the same thing with a simpler example (blinky from
C:\Keil\ARM\Boards\Embedded Artists\LPC3131\Blinky) with the same
result.&lt;/p&gt;

&lt;p&gt;
I don&amp;#39;t think that there is cache coherency issues since blinky
code is only 800 Bytes long.&lt;/p&gt;

&lt;p&gt;
Maybe am I totally wrong with the above steps. Do you have any
idea to achieve my goal ?&lt;/p&gt;

&lt;p&gt;
Best reagards&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/115217?ContentTypeID=1</link><pubDate>Thu, 17 Sep 2009 18:11:07 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a26cb610-6ad4-41a6-bb66-c63bc881ac11</guid><dc:creator>John Linq</dc:creator><description>&lt;p&gt;&lt;p&gt;
Maybe see the below link.&lt;/p&gt;

&lt;p&gt;
&lt;i&gt;RE: How to use MMU?&lt;br /&gt;
by Marcus Harnisch&lt;/i&gt;&lt;br /&gt;
&lt;a href="http://www.keil.com/forum/docs/thread14771.asp"&gt;http://www.keil.com/forum/docs/thread14771.asp&lt;/a&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/103425?ContentTypeID=1</link><pubDate>Thu, 17 Sep 2009 08:05:06 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7c5146bd-4042-4874-92bb-714a3f6723a2</guid><dc:creator>while ();</dc:creator><description>&lt;p&gt;&lt;p&gt;
If you just need instruction cache then blinky will be enough, for
data cache there is some work to be done, and if you don&amp;#39;t need it
then Blinky is all you need.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/77757?ContentTypeID=1</link><pubDate>Thu, 17 Sep 2009 06:50:29 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7d22c110-7644-416e-818a-d7915b085d5e</guid><dc:creator>bbad </dc:creator><description>&lt;p&gt;&lt;p&gt;
Thanks a lot, I need to update my version of ARM MDK to have the
blinky example with I-cache enabled.&lt;/p&gt;

&lt;p&gt;
So don&amp;#39;t I need to deal with MMU Table ?&lt;/p&gt;

&lt;p&gt;
I will look further for D-cache usage, but I think my application
will not benefit of D-cache.&lt;/p&gt;

&lt;p&gt;
Best regards&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How to enable I-cache and D-cache on LPC313x ?</title><link>https://community.arm.com/thread/56825?ContentTypeID=1</link><pubDate>Thu, 17 Sep 2009 05:17:45 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:d1635cb3-e214-4880-9174-9806b44e1f89</guid><dc:creator>while ();</dc:creator><description>&lt;p&gt;&lt;p&gt;
Keil example for Embedded Artists LPC3131 board (can be found in
folder Keil\ARM\Boards\Embedded Artists\LPC3131) has procedure for
enabling instruction cache in startup, for Data cache you will have
to look at ARM9 core documentation on how to use it.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>