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How Debugger/Breakpoint works ?

Hi Guys,
May be very basic question.
I want to understand how JTAG debugger and Break point works.

Can any one help here...?

Abhijit Dhopate

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  • Hi,

    if you want to know this in detail you should read the ARM Documentation on http://www.arm.com

    In general (examples are for the Command Line in Debug Mode):

    Hardware Breakpoint, Address Breakpoint in Flash:
    A special Unit (2 on ARM7/9, 6 on Cortex-M3) has Address Comparators. If a BP is set and the Address is reached, the Core stops and tells the debugger (ULINK, JLink) the reason.

    BS main
    

    Soft BPs, Address BP in RAM:
    Additionally in RAM the Software BP can be used. This can be an Invalid Instruction (then one HW BP on the Fault Handler is needed) or a BP Instruction

    bkpt   (arg)
    

    Access BP:
    If a memory location is read or written a BP can be defined for that. On ARM7/9 there are the 2 Units, the Cortex-M3 has 4 independant Units for this.

    1. READ, WRITE or READWRITE access:
    - up to 4 BPs can be set

    BS READ myvar
    BS WRITE myvar
    BS READWRITE myvar
    

    2. READ, WRITE or READWRITE on specific data access:
    - up to 2 BPs can be set

    BS READ myvar == 0x55
    BS WRITE myvar == 0x55
    BS READWRITE myvar == 0x55
    

    Of course one with data and 2 without data can be set.
    The Watch Unit is also used to emit Data of memory locations to be traced in the Logic analyzer.

    ---
    There are some BP possibillities I left out, they have to do with Address Ranges and are very complex. For them you'd have to read the manual.

    ---
    Does this help? I think this is what you need for your debugging work.

    .
    BR,
    /th.

Reply
  • Hi,

    if you want to know this in detail you should read the ARM Documentation on http://www.arm.com

    In general (examples are for the Command Line in Debug Mode):

    Hardware Breakpoint, Address Breakpoint in Flash:
    A special Unit (2 on ARM7/9, 6 on Cortex-M3) has Address Comparators. If a BP is set and the Address is reached, the Core stops and tells the debugger (ULINK, JLink) the reason.

    BS main
    

    Soft BPs, Address BP in RAM:
    Additionally in RAM the Software BP can be used. This can be an Invalid Instruction (then one HW BP on the Fault Handler is needed) or a BP Instruction

    bkpt   (arg)
    

    Access BP:
    If a memory location is read or written a BP can be defined for that. On ARM7/9 there are the 2 Units, the Cortex-M3 has 4 independant Units for this.

    1. READ, WRITE or READWRITE access:
    - up to 4 BPs can be set

    BS READ myvar
    BS WRITE myvar
    BS READWRITE myvar
    

    2. READ, WRITE or READWRITE on specific data access:
    - up to 2 BPs can be set

    BS READ myvar == 0x55
    BS WRITE myvar == 0x55
    BS READWRITE myvar == 0x55
    

    Of course one with data and 2 without data can be set.
    The Watch Unit is also used to emit Data of memory locations to be traced in the Logic analyzer.

    ---
    There are some BP possibillities I left out, they have to do with Address Ranges and are very complex. For them you'd have to read the manual.

    ---
    Does this help? I think this is what you need for your debugging work.

    .
    BR,
    /th.

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