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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>ssp buffer lpc2388</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/25004/ssp-buffer-lpc2388</link><description> 
Hey. 

 
I am trying to setup a communication line between to lpc2388, by
using ssp0 (as spi), where I have 1 slave and 1 master. 

 
When I send (master), a write to the fifo buffer (8x16 bits), and
it work fine. 

 
But when I try to read it (on the</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: ssp buffer lpc2388</title><link>https://community.arm.com/thread/103021?ContentTypeID=1</link><pubDate>Sat, 04 Apr 2009 11:36:19 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:db7128e5-adc0-49a2-90ac-e835f074f95d</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
I did not write about master and slave, but about receiver, since
both sides of a SPI transfer are both senders and receivers.&lt;/p&gt;

&lt;p&gt;
In your case, you ignore the transfers from slave to master. That
is ok. But have you code that takes care of the receive timeout
interrupt in your slave?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ssp buffer lpc2388</title><link>https://community.arm.com/thread/77330?ContentTypeID=1</link><pubDate>Sat, 04 Apr 2009 11:12:21 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a8dd9685-a74a-4184-ae27-90bd97c421a5</guid><dc:creator>Soeren Christensen</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi.&lt;/p&gt;

&lt;p&gt;
Communication is only from master to slave, and it is up to the
master to pick up all the data.&lt;/p&gt;

&lt;p&gt;
My ISR is beeing executed whed the buffer is half empty, which is
working finde.&lt;/p&gt;

&lt;p&gt;
The problem is maybe master.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ssp buffer lpc2388</title><link>https://community.arm.com/thread/55787?ContentTypeID=1</link><pubDate>Sat, 04 Apr 2009 09:28:35 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e2efa6cc-0db9-486f-a8f7-7a6c89668458</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
The receiver will issue a FIFO interrupt when the FIFO is (at
least) half-full.&lt;/p&gt;

&lt;p&gt;
If you stop sending data, then the receiver will get a receiver
timeout interrupt, to let you pick up any remaining words in the
FIFO.&lt;/p&gt;

&lt;p&gt;
Are you checking for both these conditions in the ISR?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>