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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/24836/spi_eeprom-interface-with-lpc2114</link><description> 
Hi all, 

 
I had written a code to interface 25c160 (SPI EEPROM) with
lpc2114. I used proteus for simulation. But when i was de-bugging my
code in keil, S0SPDR register is not taking any values.I am not able
to understand what went wrong.... 
I am</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/152879?ContentTypeID=1</link><pubDate>Wed, 04 Nov 2009 06:20:42 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:4924b03d-0798-4364-88ef-eeee34c2765b</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
I don&amp;#39;t know the correct manufacturer, but I looked at the
following Microchip datasheet (25AA160/25LC160/25C160):&lt;br /&gt;
&lt;a href="http://ww1.microchip.com/downloads/cn/DeviceDoc/cn011219.pdf"&gt;ww1.microchip.com/.../cn011219.pdf&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
&amp;Acirc;&amp;sect;2.1 contains:&lt;br /&gt;
&amp;quot;A low-to-high transition on CS after a valid write&lt;br /&gt;
sequence initiates an internal write cycle.&amp;quot;&lt;/p&gt;

&lt;p&gt;
&amp;Acirc;&amp;sect;3.2 contains:&lt;br /&gt;
&amp;quot;The read operation is terminated&lt;br /&gt;
by raising the CS pin (Figure 3-1).&amp;quot;&lt;/p&gt;

&lt;p&gt;
&amp;Acirc;&amp;sect;3.3 contains:&lt;br /&gt;
&amp;quot;After all eight bits of the instruction are ransmitted,&lt;br /&gt;
the CS must be brought high to set the write&lt;br /&gt;
enable latch. If the write operation is initiated immediately&lt;br /&gt;
after the WREN instruction without CS being&lt;br /&gt;
brought high, the data will not be written to the array&lt;br /&gt;
because the write enable latch will not have been&lt;br /&gt;
properly set.&amp;quot;&lt;/p&gt;

&lt;p&gt;
&amp;Acirc;&amp;sect;3.3 also contains:&lt;br /&gt;
&amp;quot;For the data to be actually written to the array, the CS&lt;br /&gt;
must be brought high after the Least Significant bit (D0)&lt;br /&gt;
of the nth data byte has been clocked in.&amp;quot;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/152094?ContentTypeID=1</link><pubDate>Wed, 04 Nov 2009 05:47:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:bee88811-43ab-490b-a10a-cdcbedda02ff</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Can you give links to the document(s) that said that, and the
specific point(s) at which it was said?&lt;/p&gt;

&lt;p&gt;
It appears to contradict Per&amp;#39;s quotes - so perhaps Per could also
give references?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/152880?ContentTypeID=1</link><pubDate>Wed, 04 Nov 2009 05:20:35 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:0b8c4df7-776c-4371-804d-a6b36f08b8fb</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi Per Westermark,&lt;br /&gt;
I got my answer....thanks a lot........&lt;/p&gt;

&lt;p&gt;
pavan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/152093?ContentTypeID=1</link><pubDate>Tue, 03 Nov 2009 23:20:18 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:c69d8450-7da6-41d0-a29d-bbd4988e5555</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
One note in the datasheet is:&lt;br /&gt;
&amp;quot;A low-to-high transition on CS after a valid write&lt;br /&gt;
sequence initiates an internal write cycle.&amp;quot;&lt;/p&gt;

&lt;p&gt;
Another is:&lt;br /&gt;
&amp;quot;The read operation is terminated&lt;br /&gt;
by raising the CS pin (Figure 3-1).&amp;quot;&lt;/p&gt;

&lt;p&gt;
A third note:&lt;br /&gt;
&amp;quot;After all eight bits of the instruction are ransmitted,&lt;br /&gt;
the CS must be brought high to set the write&lt;br /&gt;
enable latch. If the write operation is initiated immediately&lt;br /&gt;
after the WREN instruction without CS being&lt;br /&gt;
brought high, the data will not be written to the array&lt;br /&gt;
because the write enable latch will not have been&lt;br /&gt;
properly set.&amp;quot;&lt;/p&gt;

&lt;p&gt;
But back to my initial comment. If you get a spurious clock cycle,
and don&amp;#39;t toggle CS - how will you then get the chip to synchronize
again, so that it knows which clock cycle that represents the
transfer of the first bit of a command or address or data byte?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/151335?ContentTypeID=1</link><pubDate>Tue, 03 Nov 2009 17:33:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f37cb7b2-fb20-422e-b2de-9de5ed433b5e</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
hi,&lt;br /&gt;
yes....i had gone through the data sheet of the memory block and some
app notes., they said that CS can be grounded if a single memory
element was in operation.&lt;/p&gt;

&lt;p&gt;
pavan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/150738?ContentTypeID=1</link><pubDate>Tue, 03 Nov 2009 06:02:45 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e043756f-efd6-436c-b558-6e5c18ca7a40</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;&amp;quot;because all you want is to make CS pin low when ever you use
that memory block&amp;quot;&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
Are you sure?&lt;/p&gt;

&lt;p&gt;
What if the device relies upon seeing a falling edge on CS...?&lt;/p&gt;

&lt;p&gt;
Don&amp;#39;t make assumptions - do what the &lt;b&gt;Datasheet&lt;/b&gt; tells
you!&lt;/p&gt;

&lt;p&gt;
(so my question to you could be re-phrased as, &lt;i&gt;&amp;quot;have you
confirmed in the datasheet that holding CS low is supported&amp;quot;&lt;/i&gt;)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/146475?ContentTypeID=1</link><pubDate>Tue, 03 Nov 2009 05:48:23 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:3b96f458-3636-4ad1-9d7a-b4e337659b11</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
And you are sure that you may not get out-of-sync in your bit
train if you have no way to reassert the slave select line between
commands?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/144769?ContentTypeID=1</link><pubDate>Tue, 03 Nov 2009 05:42:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:3d664ecf-8d5f-4dc7-ada3-77dee9b15862</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi andy,&lt;br /&gt;
well grounding CS pin should not pose a problem, because all you want
is to make CS pin low when ever you use that memory block (25c150 in
my case). And i am making CS low all time.....&lt;/p&gt;

&lt;p&gt;
pavan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/142481?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 23:12:06 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:0b325caa-f3c4-49d4-b7be-9f6e33c693fd</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
Are you sure that&amp;#39;s allowed?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/139401?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 17:37:39 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:18c2de2a-c9e3-4afa-bc7e-2422f23f89a5</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi Per Westermark,&lt;br /&gt;
I have grounded the CS input of the memory, i am able to see the
clock, MOSI signal.But the MISO signal remains unchanged(in
tri-state). I am protues to check my output.&lt;br /&gt;
pavan&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/135979?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 07:54:37 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:611bf704-a894-4c92-b17e-00b2692fb420</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Have you checked the function of the slave-select signal yet?&lt;/p&gt;

&lt;p&gt;
Does the memory see slave-select, clock and MOSI signals? Is the
memory emitting any MISO signal? Does the signals look ok - correct
levels? correct timing? correct clock phase and level?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/125861?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 07:31:02 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5895dc72-00c4-4fe7-bc8a-3fff457d2598</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
Hi,&lt;br /&gt;
can any one provide me with a working code for the same.&lt;br /&gt;
it would be very helpful.......&lt;/p&gt;

&lt;p&gt;
pavannaidu.v@gmail.com&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/115357?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 04:37:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:86c81a2e-f84a-4ea6-ae03-eff15cec3ed8</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
You have one line setting one I/O pin as output:&lt;/p&gt;

&lt;pre&gt;
IODIR0  = 0x00000400;   //SET SSEL0 AS OUTPUT;
&lt;/pre&gt;

&lt;p&gt;
You have one different pin value that seems to be used for slave
select:&lt;/p&gt;

&lt;pre&gt;
IOCLR0 = 0X00000080;
&lt;/pre&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/103583?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 04:34:31 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6ec9a4ce-1698-4623-983f-97ce26166655</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Don&amp;#39;t expect that you can read back the value you write to the
data register. Depending on design, some implementations uses a R/W
register. Some designs has one read-only register at the same address
as a write-only register.&lt;/p&gt;

&lt;p&gt;
The value you are expected to pick up after a transfer, is the
data sent from the slave. Have you made sure that all signals are
toggling as expected on the slave side? Does the slave get a
slave-select? Does the slave send out any data back?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/77892?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 03:46:22 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f6a8dd9a-036b-4f4b-b67c-d54c886808f6</guid><dc:creator>pavan kumar</dc:creator><description>&lt;p&gt;&lt;p&gt;
yeah,&lt;br /&gt;
I have done that.,&lt;/p&gt;

&lt;p&gt;
Fosc = 12Mhz, configured both Cclk and Pclk to be 12Mhz&lt;br /&gt;
The SPI clock(S0SPCCR = 0x78) was configured at 100Khz.&lt;/p&gt;

&lt;p&gt;
i tried to debug the code but the S0SPDR register is not seen
taking any values!!!!1( eg., even if i forced S0SPDR = 0xAA, it was
showing S0SPDR=0x00 in the SPI peripheral window)......&lt;/p&gt;

&lt;p&gt;
i dont know what to do know?????&lt;/p&gt;

&lt;p&gt;
pavan.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SPI_EEPROM INTERFACE WITH LPC2114</title><link>https://community.arm.com/thread/57172?ContentTypeID=1</link><pubDate>Mon, 02 Nov 2009 01:26:01 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:3f2e477c-f0d4-4885-9db6-71d2880e2a12</guid><dc:creator>Tamir Michael</dc:creator><description>&lt;p&gt;&lt;p&gt;
are you sure the peripheral clock is setup correctly...? if not,
the S0SPCCR is invalid.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>