I want to design my code space as two halves, one part is 48KB which is resident in RAM and the other part 16KB is dynamically swappable based on the operations 8051 is required to perform. How should I organize and build my code?
1.) I am guessing I will need to design my own dynamic code page loader. I have an indirect ability to write to code space RAM structure using an external h/w piece.
2.) The problem for me is how should I organize my code and build it in this case since, I can have several pages of swappable code? Should I build each of these swappable 16KB code as absolute-segment libraries and assign them the upper 16KB address space? How about the data segments for these swappable code? Do I need to limit the range there as well?
Any insight will be helpful. Thanks.
This question keep popping up from people that have no idea what a '51 is intended for.
If you want replaceable code use a (non-Harvard) processsor intended for that.
Erik
Thanks for the responses.
This is a 3rd ver. of the product. The feature set has outgrown the code RAM we have. Also, we cannot choose any other processor because of schedule and cost reasons.
So, one of the solutions we started thinking about was to swap in code pages as they were needed specially for code that did not have real-time requirements. Essentially, we would like to partition code into two parts, one is going to be resident with a code page loader logic and other part can be swapped in from flash using some special h/w when needed. To make that work, we are trying to figure out how to build code for resident part and for the different swappable pages.
But your proposed "solution" sounds like it will be neither cheap nor quck to implement - if it can be made to work at all!
The fact of the matter is that you have long outgrown this processor!
Your immediate effort might be better spent in trying to reduce the size of the existing code - while you make an urgent start working on a re-design that can actually accommodate your requirements!
You might want to take advantage of the Huge memory module and startup code. Within that 'huge' memory model is the ability to bank-switch by setting port I/O to chip-enable (or a higher than the 16-bit address to the RAM) the memory bank in which you need to access. The lower 64K address space and map can stay the same, but the port I/O can swap which chip it needs to read/write from.
The problem then becomes working around the Harvard architecture. But since it is RAM, then you should be able to point to that lower portion of the chip and do a movx instruction.
I might be way off base, but that is what I was thinking as I read this thread.
--Cpt. Vince Foster 2nd Cannon Place Fort Marcy Park, VA
This is a 3rd ver. of the product. The feature set has outgrown the code RAM we have. Also, we cannot choose any other processor because of schedule and cost reasons. what is code RAM, this is a '51
erik,
You can use RAM instead of ROM/PROM/etc if you wire it up that way. But it will take some intervention to execute out of this RAM. You would have to load up the RAM wired into code-space either through some external means or a boot-loader in ROM/PROM/etc.
Even though the '51 is not a Von Neumann architecture, you can execute from RAM space (that is wired to be in code-space).
Right. We have h/w hooks to download code from flash into a RAM structure before 8051 execution begins.
One option we are considering is to build code as multiple banks, but, have the h/w alias multiple bank addresses to the same RAM structure. Then, manage the "shared" code RAM from the resident code making sure the intended bank code is physically present in the shared RAM before it is called.
I know we are going over hoops to make it work. But, we are limited due to cost and schedule reasons for the current design. And, we have already optimized the C-code as much as we think is possible.
Why Not stay with Standard Banking The compiler support this directly.
Cannot add more RAM structures for cost reasons/margin.
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