<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Byte ordering in C8051F020</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/24414/byte-ordering-in-c8051f020</link><description> 
Hi, Can anyone tell me what is the byte ordering in C8051F020
SiLabs Microcontroller? Whether it is a Little Endian or Big
Endian? 

 
Thanks 
 </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Byte ordering in C8051F020</title><link>https://community.arm.com/thread/89898?ContentTypeID=1</link><pubDate>Thu, 30 Jul 2009 08:09:41 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:39af173f-32f7-452a-b554-777aa06cc622</guid><dc:creator>Advanced Zeusti</dc:creator><description>&lt;p&gt;&lt;p&gt;
HI.&lt;/p&gt;

&lt;p&gt;
&amp;lt;quote&amp;gt;&lt;br /&gt;
the only &amp;#39;byte ordering&amp;#39; there is in the actual controller is for the
mov dptr,# (the only 16 bit operation in the processor)&lt;br /&gt;
&amp;lt;/quote&amp;gt;&lt;/p&gt;

&lt;p&gt;
and ajmp/ljmp for dst adress&lt;/p&gt;

&lt;p&gt;
and acall/lcall for ret addr on stck&lt;/p&gt;

&lt;p&gt;
and bibel tells u about it to.&lt;/p&gt;

&lt;p&gt;
Always yo&amp;#39;re freind.&lt;/p&gt;

&lt;p&gt;
Zeusti.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Byte ordering in C8051F020</title><link>https://community.arm.com/thread/103302?ContentTypeID=1</link><pubDate>Thu, 30 Jul 2009 07:18:15 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1df0cbe8-ba86-45ec-a219-9d6012b7f210</guid><dc:creator>&amp;#178;erik malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;There are, however, some other 16-bit SFRs&lt;/i&gt;&lt;br /&gt;
OK, but they are not &amp;quot;in the processor&amp;quot; and the &amp;#39;byte ordering&amp;#39; is
not mandatory. Yes it is &amp;#39;standardized&amp;#39; for the &amp;#39;traditional, but
were I to design a chip (fat chance) with a 16 bit register I could
&lt;i&gt;legally&lt;/i&gt; put the high and low byte SFRs in any order, even far
apart, should I wish.&lt;/p&gt;

&lt;p&gt;
also there are no &amp;quot;16-bit SFRs&amp;quot; but some interface registers that
are associated with 2 (8 bit) SFRs to make a 16 bit
&lt;b&gt;register&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Byte ordering in C8051F020</title><link>https://community.arm.com/thread/89896?ContentTypeID=1</link><pubDate>Thu, 30 Jul 2009 07:02:48 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5794517f-befe-445f-b4a0-47d6ab346c3d</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
There are, however, some other 16-bit SFRs.&lt;/p&gt;

&lt;p&gt;
You have to load the bytes individually - but, again, check in the
&lt;b&gt;Datasheet&lt;/b&gt; for the order.&lt;/p&gt;

&lt;p&gt;
Note that Keil&amp;#39;s &lt;b&gt;sfr16&lt;/b&gt; does &lt;b&gt;&lt;i&gt;not&lt;/i&gt; necessarily&lt;/b&gt;
match a specific chip&amp;#39;s required order...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Byte ordering in C8051F020</title><link>https://community.arm.com/thread/56530?ContentTypeID=1</link><pubDate>Thu, 30 Jul 2009 06:48:55 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f4470d5d-730e-4e7a-be19-5c306fcbd98e</guid><dc:creator>&amp;#178;erik malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;Can anyone tell me what is the byte ordering in C8051F020
SiLabs Microcontroller&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
Whatever you want. However you will obviously let your
assembler/compiler/linker decide for you.&lt;/p&gt;

&lt;p&gt;
the only &amp;#39;byte ordering&amp;#39; there is in the actual controller is for
the mov dptr,# (the only 16 bit operation in the processor) and the
bible tell you what that is.&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Byte ordering in C8051F020</title><link>https://community.arm.com/thread/56527?ContentTypeID=1</link><pubDate>Wed, 29 Jul 2009 23:44:07 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f88ebab5-2534-4f26-852b-1f5f3ec5326e</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
It&amp;#39;s an 8-bit controller - so it deals only in bytes. Any
multi-byte operations have to be entirely synthesised by the
&lt;b&gt;compiler&lt;/b&gt; - so the answer to your question will be found in the
&lt;b&gt;compiler &lt;i&gt;Manual&lt;/i&gt;&lt;/b&gt;&lt;/p&gt;

&lt;p&gt;
&lt;a href="http://www.keil.com/support/man/docs/c51/c51_ap_datastorage.htm"&gt;http://www.keil.com/support/man/docs/c51/c51_ap_datastorage.htm&lt;/a&gt;&lt;br /&gt;

&lt;a href="http://www.keil.com/support/man/docs/c51/c51_ap_2bytescalar.htm"&gt;http://www.keil.com/support/man/docs/c51/c51_ap_2bytescalar.htm&lt;/a&gt;&lt;br /&gt;

&lt;a href="http://www.keil.com/support/man/docs/c51/c51_ap_4bytescalar.htm"&gt;http://www.keil.com/support/man/docs/c51/c51_ap_4bytescalar.htm&lt;/a&gt;&lt;br /&gt;

etc...&lt;/p&gt;

&lt;p&gt;
The exception is any multi-byte SFRs - which will be defined in
the chip&amp;#39;s &lt;b&gt;Datasheet&lt;/b&gt;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>