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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>UART TX FIFO</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/24000/uart-tx-fifo</link><description> 
Hello, 
Using an LPC2400 family with UART FIFOs enabled (RX &amp;amp; RX) does
this mean that in entire TX FIFO (16 bytes) must be filled in order
to have data placed on the bus, or does that happen every predefined
period? I looked in the data sheet of the</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/125365?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:24:41 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ae5434ff-78f8-4130-89b1-06c5e2ba311a</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
ho sorry - the FIFO and the shift register are separate entities!
ok now I get it. thanks.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/125361?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:20:21 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e4d897b8-8c06-4df0-8e5c-34bcf1b4f754</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
I am sorry for bothering you again, but I still don&amp;#39;t understand
precisely what the THRE interrupt is all about: If I read the
documentation, I understand that it means that there is room for more
data (1 byte at least?). so, how can I pump data into it without
knowing the condition of the shift register? isn&amp;#39;t it so that the
shift register is 16 bytes in size? the THR is merely a register;
what is the FIFO only has 1 free slot when the THRE interrupt
occured? thanks.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/114808?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:12:58 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b093df63-a6dd-4a97-a6f7-b15161e295b0</guid><dc:creator>Per Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
If you wait until you get a TEMT (Transmitter empty) then your
UART will stop while waiting for more food. It is better that you
start filling it when you see the THRE bit - that means that the last
byte of the FIFO has been moved into the outgoing shift register and
you now have one character time period to start adding more data to
not get a stalled transmitter.&lt;/p&gt;

&lt;p&gt;
Is there any reason why you prefer a loop to poll the status
instead of just using a ring buffer and have an interrupt react and
refill the FIFO?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/125364?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:07:29 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:48e13556-4335-48a8-b6da-cd848607b170</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
yes of course, I understand what you mean. thanks a lot.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/101762?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:06:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1ba9723b-f702-4f57-a189-440dda5ec0c4</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
ok, I can poll bit6 in line status register, which indicated both
the holding register and the short register empty (hence, the THRE
interrupt is not necessary). then I can place 16 bytes in hardware,
not?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/114807?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 07:06:25 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:315c6617-f866-46c7-83e1-485bca2189a7</guid><dc:creator>Per Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
You write your UART interrupt so that if it sees the THRE flag,
you do multiple inserts into the transmit holding register. If you
add 16 characters for every THRE interrupt, the load on the processor
will be significantly lower than running without the FIFO.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/101761?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 06:59:20 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e9825837-da67-4a71-9765-e0c03c0007ec</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
I understand - thanks. sorry for asking, I never worked with a
FIFO UART before (only not FIFOed). anyway, the data sheet says
this:&lt;/p&gt;

&lt;pre&gt;
A THRE interrupt is set immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty.
&lt;/pre&gt;

&lt;p&gt;
what does that mean if I need to place a buffer of, say, 1000
bytes on the bus? how do I get that done smoothly?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/89647?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 06:50:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a2ac6e83-7ecd-432f-bafa-b7bb7d550dc6</guid><dc:creator>Per Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
You don&amp;#39;t need to fill the transmit FIFO full to start
transmitting. It will automatically transmit.&lt;/p&gt;

&lt;p&gt;
There is a bit of special logic that will delay the THRE interrupt
to give you time to fill in more characters in the FIFO. After you
have had at least two characters in the TX FIFO at the same time, the
next THRE will come immediately, to inform you that the TX FIFO needs
more data.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: UART TX FIFO</title><link>https://community.arm.com/thread/55743?ContentTypeID=1</link><pubDate>Fri, 27 Mar 2009 06:37:55 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:de0a1af3-b7d9-4f37-8fa2-bab830fcafb2</guid><dc:creator>Cactus Blip</dc:creator><description>&lt;p&gt;&lt;p&gt;
I forget to mention that I don&amp;#39;t use any control signaling - only
RX &amp;amp; TX.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>