Hello all, I have just recovered my STR9 from a fatal startup crash due to invalid setting of the SCU_CLKCNTR. My PLL generates a 48 MHz clock, and the source of the problem was the APBDIV bit field: dividing RCLK (=48 MHz) by 2 (so that APB is fed by a 24 MHz clock) is presumably invalid. But why is that? I have re-read the clocks chapter in the reference guide, to no avail.
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