<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>SFR addressing question</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/22752/sfr-addressing-question</link><description> 
Where as all defined SFR&amp;#39;s (IE ones that aren&amp;#39;t reserved) fit
within the range of S:080-S:0FF. So (considering the available IP
variants) how can one address or even access S:000-S:07F or
S:100-S:1FF? There doesn&amp;#39;t appear to be a mechanism listed in</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/135246?ContentTypeID=1</link><pubDate>Tue, 08 Jan 2008 07:06:49 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:98d5f84e-a562-4f9c-9289-2e170783b48c</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
Don&amp;#39;t forget i960 or XScale or the StrongARM that they bought and
produced.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/124342?ContentTypeID=1</link><pubDate>Tue, 08 Jan 2008 05:45:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1b7e0517-84e6-4e3a-bbf7-9cb2b7d92804</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
I think Intel now see the 386 and 486 as &amp;quot;microcontrollers&amp;quot;&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/113524?ContentTypeID=1</link><pubDate>Tue, 08 Jan 2008 05:33:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a1efb757-4396-4e36-a82f-fae5c4bc2c72</guid><dc:creator>stephen phillips</dc:creator><description>&lt;p&gt;&lt;p&gt;
I think Intel in general has given up on micro controllers. I
guess the mystery will remain, a mystery. I suppose they designed in
the ability to have 512 SFR bytes but never implemented it.&lt;/p&gt;

&lt;p&gt;
Stephen&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/100096?ContentTypeID=1</link><pubDate>Sun, 06 Jan 2008 08:55:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:89fdad89-667f-4b97-9c29-1d78ca94526f</guid><dc:creator>Jon Ward</dc:creator><description>&lt;p&gt;&lt;p&gt;
From what I recall of the 251 (I was at Keil when we started
working with Intel on tools for it), Intel never specified a way to
access these &amp;quot;extended&amp;quot; SFRs. There was no instruction in the
instruction set for it and none were ever defined. After the 80C251Sx
and the 930 devices, Intel gave up on further 251 development.&lt;/p&gt;

&lt;p&gt;
Jon&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/100108?ContentTypeID=1</link><pubDate>Fri, 04 Jan 2008 08:17:27 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:b7bf8fac-fd01-48e5-8745-ec4d9f2f0642</guid><dc:creator>Gp F</dc:creator><description>&lt;p&gt;&lt;p&gt;
Your assumption is correct: the compiler/assembler (for example
CX51) decides when to use a prefixed instruction based on the sfr
address. The same is true for bits of extended sfrs.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/88781?ContentTypeID=1</link><pubDate>Fri, 04 Jan 2008 08:08:59 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a43cda50-7ff9-475d-9845-db17f46e2bfa</guid><dc:creator>stephen phillips</dc:creator><description>&lt;p&gt;&lt;p&gt;
Really? So basically it would be up to the compiler and the way it
handled sfr definition? This makes sense but, Intel and Temic/Atmel
user guides really were vague about what the instruction encoding was
(really vague).&lt;/p&gt;

&lt;p&gt;
So for S:000 - S:07F likely it is a different extension, OK that
makes sense I&amp;#39;ll have to recheck the instruction matrix and
information it has regarding that.&lt;br /&gt;
Thank you now I have an idea of where to look.&lt;/p&gt;

&lt;p&gt;
Stephen&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: SFR addressing question</title><link>https://community.arm.com/thread/49209?ContentTypeID=1</link><pubDate>Fri, 04 Jan 2008 06:34:09 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:da2a8022-c786-4a87-b3bf-798796484b01</guid><dc:creator>Gp F</dc:creator><description>&lt;p&gt;&lt;p&gt;
The sfr&amp;#39;s with addresses 0x1nn are usually accessed by using
instruction extensions, that is - for example on a C51MX device by
using a prefixed mov instruction:&lt;/p&gt;

&lt;pre&gt;
       0xE5,0xF0:  MOV  A,0xF0 - regular 51 sfr.
  0xA5,0xE5,0xF0:  MOV  A,0xF0 - actually accesses S:0x1F0
&lt;/pre&gt;

&lt;p&gt;
&lt;br /&gt;
Such extensions exist on 80C51MX/MXP, SmartMX and also some C251
devices.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>