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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>RAM contents after WDT reset</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/22305/ram-contents-after-wdt-reset</link><description> 
Hi, 

 
I need to place some data in RAM and then use the watchdog to
force a device reset. After the device reset, I will read the same
locations in RAM to determine what to do. This has to do with a
bootloader project. 

 
However, I am running into</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: RAM contents after WDT reset</title><link>https://community.arm.com/thread/76308?ContentTypeID=1</link><pubDate>Mon, 19 May 2008 23:59:37 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:144de81b-9d81-42a5-83b9-6ed9dabdcdc3</guid><dc:creator>Oyvind Kaurstad</dc:creator><description>&lt;p&gt;&lt;p&gt;
Thank you! Now you mention it, I had actually read that
previously, but I&amp;#39;d forgotten all about it.&lt;/p&gt;

&lt;p&gt;
I feel slightly ashamed now... :-)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: RAM contents after WDT reset</title><link>https://community.arm.com/thread/49918?ContentTypeID=1</link><pubDate>Mon, 19 May 2008 22:14:54 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8d517e96-fe8b-4735-8b28-48ecb0911510</guid><dc:creator>Robert &amp;#160;</dc:creator><description>&lt;p&gt;&lt;p&gt;
The behavior you are seeing is completely normal for all NXP
LPC2000 devices and has to do with the on-chip SRAM controller.&lt;/p&gt;

&lt;p&gt;
Here are a few lines from the LPC2300 user manual:&lt;/p&gt;

&lt;p&gt;
The SRAM controller incorporates a write-back buffer in order to
prevent CPU stalls during back-to-back writes. The write-back buffer
always holds the last data sent by software to the SRAM. The data is
only written to the SRAM when software does another write. After a
&amp;quot;warm&amp;quot; chip reset, the SRAM does not reflect the last write
operation. Two identical writes to a location guarantee that the data
will be present after a Reset. Alternatively, a dummy write operation
before entering idle or power-down mode will similarly guarantee that
the last data written will be present after a subsequent Reset.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>