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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/21684/can-at89c2051-be-used-as-a-slave-device-for-spi</link><description> 
Hi, I have to design a circuit using AT89C51 with no hardware SPI
and use it as SPI master. The SPI slave device I am using is
AT89C2051 which is controlling the RTC chip DS1307 using I2C
protocol. When ever a particular event occurs the AT89C2051 records</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/138442?ContentTypeID=1</link><pubDate>Tue, 29 May 2007 07:56:55 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e4ca81c9-cfb9-4d44-b369-92de5ba45df5</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
look at NXP LPC9xx series sub $1 sub 30 pins&lt;/p&gt;

&lt;p&gt;

&lt;a href="http://www.nxp.com/cgi-bin/catalog/catalog.pl/282/50809/index.html#50809"&gt;www.nxp.com/.../index.html&lt;/a&gt;&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/130163?ContentTypeID=1</link><pubDate>Mon, 28 May 2007 03:34:09 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:22095226-72f3-4e38-93bc-1715ec426fbb</guid><dc:creator>Raghu Nandan</dc:creator><description>&lt;p&gt;&lt;p&gt;
Thanks for your reply. I would like to know is there any micro
controller which is cost effective and minimum number of pins such as
AT89C2051 with hardware SPI to implement a slave on the device.
Raghu.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/123843?ContentTypeID=1</link><pubDate>Fri, 25 May 2007 11:00:13 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:89c81d18-c729-471a-a4e1-afa93a24a319</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
I missed that the OP was discussing bit-bagging for both master
and slave side.&lt;/p&gt;

&lt;p&gt;
That would require the master to run _very_ slow to make sure no
bits are lost in either direction.&lt;/p&gt;

&lt;p&gt;
By the way: How I hate when the blasted site complains about my
email address - at the same time I can hear it bing, receiving
mails... If Keil could just permanently mark an email OK - especially
if it is an email address that I have managed to mail them from - and
they have managed to mail me back on...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/112890?ContentTypeID=1</link><pubDate>Fri, 25 May 2007 08:42:37 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:70366657-de6c-4525-b861-80a13c3c563c</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;There are not too much problems with any timing errors for a
SW-driven &lt;b&gt;master&lt;/b&gt;. It is trivial to make sure it isn&amp;#39;t too
fast.&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
I agree, but what about the bit-banged slave. a bit-banged slave
must stop whatever it is doing (time critical or not) to receieve tha
data. Yes, you may be able with an inverter or two to make it a bit
less time consuming using interrupts, but there will still bee some
potential timing problems with the &amp;quot;do it NOW&amp;quot; requirements a
bit-banged slave, by definition, must have.&lt;/p&gt;

&lt;p&gt;
Had it not been for the plethora of HW SPI derivatives there is, I
might have gone into a more detailled discussion of the many problems
with a bit-banged slave, but I consider it futile to &amp;#39;fight&amp;#39; bit-bang
for a slave when getting the chip from another corner of the drawer
solves it in a breeze. There is no shortage of the other features you
can find in HW SPI chips - and at &amp;lt; $1.&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/99246?ContentTypeID=1</link><pubDate>Fri, 25 May 2007 07:34:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a47dafa4-353e-4ea6-af82-ab11bf2ab01a</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
There are not too much problems with any timing errors for a
SW-driven master. It is trivial to make sure it isn&amp;#39;t too fast.&lt;/p&gt;

&lt;p&gt;
Unless large volumes of data needs to be transmitted, or the data
arrives in bursts larger than the buffer size, a SW master will be
fast enough for quite a lot of jobs. If it isn&amp;#39;t, then it isn&amp;#39;t
unlikely that a &amp;#39;51 chip with hw SPI isn&amp;#39;t fast enough either.&lt;/p&gt;

&lt;p&gt;
There is a huge difference between bit-banging a UART or a Dallas
one-wire communication and bit-banging the master side of SPI, since
there is a separate wire for the clock. Jitter time does not matter
the slightest, as long as the transfer rate is fast enough that the
sender side doesn&amp;#39;t suffer from buffer overflow.&lt;/p&gt;

&lt;p&gt;
The amount of code to implement the master side of SPI is puny. It
takes longer to look at the data sheets of an alternative uC than it
takes to implement the few code lines and test them.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/88350?ContentTypeID=1</link><pubDate>Fri, 25 May 2007 07:22:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8bbcc13a-9cfa-4ae2-b6e2-39c43fc2ab8b</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
you can get HW SPI for less than $1 (e.g. NXP LPC) is it worth the
fight - and the likelyhood of timing errors - to try &amp;quot;the beast&amp;quot; of a
SW SPI slave.&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Can AT89C2051 be used as a slave device for SPI</title><link>https://community.arm.com/thread/50785?ContentTypeID=1</link><pubDate>Fri, 25 May 2007 05:51:21 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:120b9a24-e141-482e-ab2d-dee40d213fd4</guid><dc:creator>ImPer Westermark</dc:creator><description>&lt;p&gt;&lt;p&gt;
It is trivial to implement a SPI master in software.&lt;/p&gt;

&lt;p&gt;
It is a lot harder to implement a SPI slave in software, since the
slave must be fast enough to not miss individual bits.&lt;/p&gt;

&lt;p&gt;
What approximate baudrate do you need to be able to transfer the
generated data?&lt;/p&gt;

&lt;p&gt;
Unless you are going to use long signal lines between the two
chips, the easiest thing is to do emit the bits of each word transfer
either in a loop or unrolled for the individual bits. Since SPI is
clocked by a separate signal, you don&amp;#39;t even have to worry about an
interrupt arriving and increasing the length of a bit cycle.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>