<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>size of an architecture depends on</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/21091/size-of-an-architecture-depends-on</link><description> 
Size of an microcontroller or processor architecture depends on
whteher the address bus or data bus or ALU or all the three 
 </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/150189?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 13:20:45 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:336ee46b-3905-4c1d-b1b7-783fbcaacbda</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
life&amp;#39;s like that!&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/141684?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 12:28:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:8b46a524-846a-4bcf-ba6a-69c9c4a98219</guid><dc:creator>Drew Davis</dc:creator><description>&lt;p&gt;&lt;p&gt;
&amp;quot;Size&amp;quot; doesn&amp;#39;t matter.&lt;/p&gt;

&lt;p&gt;
Or at least for almost any practical purpose you need to be a lot
more specific about which part of the CPU you&amp;#39;re talking about. As
this thread shows, trying to characterize an architecture with a
single scalar number is a bit too simplistic to mean much.&lt;/p&gt;

&lt;p&gt;
When people say &amp;quot;it&amp;#39;s a X-bit processor&amp;quot;, in my experience they
generally mean the width of the internal general-purpose data
registers used for computation. The address and data busses of
particular implementations often vary. Address spaces often get
complicated with segmenting / paging / banking schemes.&lt;/p&gt;

&lt;p&gt;
The Intel 8086 had a 16-bit data bus; the 8088 had an 8-bit data
bus, with the CPUs otherwise largely identical: variable length
instructions, 16-bit registers, 16-bit internal data paths, 20-bit
address bus (using segment registers internally). Most people called
both of them &amp;quot;16-bit processors&amp;quot;.&lt;/p&gt;

&lt;p&gt;
The 68000 had variable length instructions, 32 bit registers, a
16-bit data bus, and a 24-bit address bus. Internally, addresses were
32 bits, but only 24 came out, as Apple found out to their chagrin
when they switched to 68020s. Turned out a few too many programmers
were being &amp;quot;efficient&amp;quot; and using that upper byte of the address to
store data, confident in the knowledge that those bits would never
actually appear on the address bus...&lt;/p&gt;

&lt;p&gt;
ARM7s have 32-bit registers, fixed 32-bit instructions, and a
16-bit data bus, so many operations take two memory accesses. Most
people call all ARMs &amp;quot;32-bit processors&amp;quot;.&lt;/p&gt;

&lt;p&gt;
It gets complicated in detail.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/138306?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 11:41:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:436d62bd-cae3-4932-9299-30e470222047</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;A little off topic @Erik: An 8051 has 4-byte instruction(s)? By
which OpCodes? I know only 1-, 2- and 3-byte instructions for
8051.&lt;/i&gt;&lt;br /&gt;
neither do I, I got carried away typing numbers :)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/134877?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 11:04:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6ea4c99c-a11d-4932-bb31-4789888cefdf</guid><dc:creator>Martin Macher</dc:creator><description>&lt;p&gt;&lt;p&gt;
I would suggest: The width of the working register(s) is relevant
for the width of processor architecture.&lt;/p&gt;

&lt;p&gt;
Few examples:&lt;br /&gt;
*8051 ist a 8bit machine, although it has 16bit DPTR and 16bit
addressing space.&lt;br /&gt;
*Intel Pentium III ist a 32bit machine, it has also 32bit addressing
space.&lt;br /&gt;
*Intel Core2Duo ist a 64bit machine, although it has 128bit special
SSE registers (and some legacy 32bit registers!), it has only 36bit
addressing space.&lt;/p&gt;

&lt;p&gt;
&lt;i&gt;...the &amp;quot;size&amp;quot; referred to the length of the instructions which
are fetched from code memory...&lt;/i&gt; is irrelevant, as Erik already
said.&lt;br /&gt;
For example, a PIC 8bit &amp;micro;C has 14bit 16bit or 18bit opcodes
(depends on appropriate family e.g. PIC18Cxxx has 18bit opcodes).&lt;/p&gt;

&lt;p&gt;
A little off topic @Erik: An 8051 has 4-byte instruction(s)? By
which OpCodes? I know only 1-, 2- and 3-byte instructions for
8051.&lt;/p&gt;

&lt;p&gt;
Martin&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/123514?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 07:47:39 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:80edfcb8-995d-414c-b545-b76086945ea6</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;I would have thought that the &amp;quot;size&amp;quot; referred to the length of
the instructions which are fetched from code memory...&lt;/i&gt;&lt;br /&gt;
HUH?&lt;/p&gt;

&lt;p&gt;
e.g. the &amp;#39;51 has 1,2,3 and 4 byte long instructions. Most (all?)
computers I have worked with have had a variable instruction
length.&lt;/p&gt;

&lt;p&gt;
Erik&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/112488?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 07:09:57 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6e93d5f3-127d-49a7-8739-4a3efcea58f1</guid><dc:creator>Rich McCoy</dc:creator><description>&lt;p&gt;&lt;p&gt;
I would have thought that the &amp;quot;size&amp;quot; referred to the length of the
instructions which are fetched from code memory...&lt;/p&gt;

&lt;p&gt;
-=Rich=-&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/98682?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 07:02:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:983ed5ed-5136-40a0-8d01-de6c9c8610f8</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
I said, &lt;i&gt;&amp;quot;The &amp;#39;word&amp;#39; is the basic unit of data that the
processor &lt;b&gt;processes&lt;/b&gt;&amp;quot;&lt;/i&gt; (emphasis added).&lt;/p&gt;

&lt;p&gt;
I think it&amp;#39;s the &lt;b&gt;processesing&lt;/b&gt; that&amp;#39;s the key word - as
already noted, the 8-bit 8051 has a 16-bit address bus; similarly the
16-bit 8086 has a 20-bit address bus, and didn&amp;#39;t the 8088 have an
8-bit &lt;i&gt;external&lt;/i&gt; data bus?&lt;/p&gt;

&lt;p&gt;
Thus the ALU width is probably the key...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/74586?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 06:54:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:31e78151-425f-4780-be4b-8ba426d2c4c8</guid><dc:creator>senthil arumugam</dc:creator><description>&lt;p&gt;&lt;p&gt;
What you said was correct, but i have a doubt regarding the below
situation?&lt;/p&gt;

&lt;p&gt;
Lets consider like this: Our address bus is small(8bit) in size
than data bus(16 bit). So by the time what may be the size of the
processor. So in determining the size of a processor no need to
consider the address bus , ALU right?&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: size of an architecture depends on</title><link>https://community.arm.com/thread/47306?ContentTypeID=1</link><pubDate>Tue, 28 Nov 2006 01:25:43 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:16192a48-8390-4ffc-8bfd-90d2fd84d2b7</guid><dc:creator>Andy Neil</dc:creator><description>&lt;p&gt;&lt;p&gt;
The &amp;quot;size&amp;quot; of a processor architecture is its &lt;b&gt;&lt;i&gt;word&lt;/i&gt;
size&lt;/b&gt;;&lt;/p&gt;

&lt;p&gt;
Thus an 8-bit processor works on an 8-bit word;&lt;br /&gt;
A 16-bit processor works on a 16-bit word;&lt;br /&gt;
etc, etc, ...&lt;/p&gt;

&lt;p&gt;
The &amp;quot;word&amp;quot; is the basic unit of data that the processor processes
- thus it will be the general register size.&lt;/p&gt;

&lt;p&gt;
The address bus is usually bigger than the word size; eg, the 8051
is an 8-bit architecture, but has a 16-bit address bus...&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>