configure PIO of ARM9 as input.

hi all,
I am Kirti Patel from india.
i am using AT91RM9200+FPGA SBC board made by darell harmon...
in this board when i read the status of the pio pins during execution ..at that time i am not getting the good response as on the pins.i.e.wrong response.and if i made changes through key pad to this particular pins at that time i did't get good response....
now in addition to this i want to start FPGA working on this board and send bitstream file through ARM9 controller.

so what i have to do??can any one help me about my problem..
Thanks.

Parents
  • This is a list of the registers associated with a GPIO port to review for how they are configured and handled at runtime:

    PIO_PER
    PIO_PDR
    PIO_PSR
    PIO_OER
    PIO_ODR
    PIO_OSR
    PIO_IFER
    PIO_IFDR
    PIO_IFSR
    PIO_SODR
    PIO_CODR
    PIO_ODSR
    PIO_PDSR
    PIO_IER
    PIO_IDR
    PIO_IMR
    PIO_ISR
    PIO_MDER
    PIO_MDDR
    PIO_MDSR
    PIO_PUDR
    PIO_PUER
    PIO_PUSR
    PIO_ASR
    PIO_BSR
    PIO_ABSR
    PIO_OWER
    PIO_OWDR
    PIO_OWSR

    Here are the steps I use in my AT91RM9200 bootloader to pump a bitstream into a Xilinx FPGA:

    • Init configuration signals.
    • Assert FPGA_PROG_B for >300ns (one tick of the system timer is ~2us) and wait for ARM_FPGA_INIT to go high (should be <5ms). If it doesn't, return timeout indication.
    • For each bit of each byte in the bitstream, take CLK_ARM_FPGA low, present the data bit, then take CLK_ARM_FPGA high to clock in the data on the rising edge.
    • Check DONE and INIT (low means CRC error), then four more clocks.
    • Assert FPGA_RST_N for >TBD (one tick of the system timer is ~2us).

Reply
  • This is a list of the registers associated with a GPIO port to review for how they are configured and handled at runtime:

    PIO_PER
    PIO_PDR
    PIO_PSR
    PIO_OER
    PIO_ODR
    PIO_OSR
    PIO_IFER
    PIO_IFDR
    PIO_IFSR
    PIO_SODR
    PIO_CODR
    PIO_ODSR
    PIO_PDSR
    PIO_IER
    PIO_IDR
    PIO_IMR
    PIO_ISR
    PIO_MDER
    PIO_MDDR
    PIO_MDSR
    PIO_PUDR
    PIO_PUER
    PIO_PUSR
    PIO_ASR
    PIO_BSR
    PIO_ABSR
    PIO_OWER
    PIO_OWDR
    PIO_OWSR

    Here are the steps I use in my AT91RM9200 bootloader to pump a bitstream into a Xilinx FPGA:

    • Init configuration signals.
    • Assert FPGA_PROG_B for >300ns (one tick of the system timer is ~2us) and wait for ARM_FPGA_INIT to go high (should be <5ms). If it doesn't, return timeout indication.
    • For each bit of each byte in the bitstream, take CLK_ARM_FPGA low, present the data bit, then take CLK_ARM_FPGA high to clock in the data on the rising edge.
    • Check DONE and INIT (low means CRC error), then four more clocks.
    • Assert FPGA_RST_N for >TBD (one tick of the system timer is ~2us).

Children
More questions in this forum