<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>AT91SAM7S256 not coming out of RESET...</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/20637/at91sam7s256-not-coming-out-of-reset</link><description> 
Okay... this may be slightly off topic... I&amp;#39;m suspecting hardware
more than software. 

 
Here&amp;#39;s the problem... I&amp;#39;ve done KEIL projects for AT91SAM7S32 and
AT91SAM7S64 boards and the hardware has always come out of reset and
started to execute code</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: AT91SAM7S256 not coming out of RESET...</title><link>https://community.arm.com/thread/112309?ContentTypeID=1</link><pubDate>Wed, 06 Sep 2006 15:16:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:90460c20-016d-4989-86e8-9f57916cf78f</guid><dc:creator>Roger Lynx</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;Do you see a problem with that math?&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
Not now.&lt;br /&gt;
:-)&lt;br /&gt;
PLL min/max seem to be okay, now.&lt;/p&gt;

&lt;p&gt;
BTW, do you wait for the PLL to settle down after programming the
MUL and DIV, I suppose you are?&lt;/p&gt;

&lt;pre&gt;
  while(!(AT91C_BASE_PMC-&amp;gt;PMC_SR &amp;amp; AT91C_PMC_LOCK));

  while(!(AT91C_BASE_PMC-&amp;gt;PMC_SR &amp;amp; AT91C_PMC_MCKRDY));
&lt;/pre&gt;

&lt;p&gt;
Is your AT91C_CKGR_PLLCOUNT sufficient for the setup time?&lt;/p&gt;

&lt;p&gt;
Then I would re-check the PLL&amp;#39;s ext. RC values. There is a new
release (v2.31) of the spreadsheet PLL calculator.&lt;/p&gt;

&lt;p&gt;
Good luck, man!&lt;br /&gt;
:-)&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: AT91SAM7S256 not coming out of RESET...</title><link>https://community.arm.com/thread/98407?ContentTypeID=1</link><pubDate>Wed, 06 Sep 2006 14:32:36 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:32ad28aa-1cb9-4c14-b9e0-bc870e4d844a</guid><dc:creator>Dave Sudolcan</dc:creator><description>&lt;p&gt;&lt;p&gt;
MCK = CRYSTAL * (MUL+1) / (DIV*2) = 20M * 1402 / 510 =
54.98Mhz&lt;/p&gt;

&lt;p&gt;
which is less than the max allowable MCK of 55 MHz, right? These
settings should make a PLLCK of ~ 110 MHz, which is in spec too,
right? I&amp;#39;m using 1 wait state for flash reads.&lt;/p&gt;

&lt;p&gt;
However, I did find out that I had violated the min input
frequency spec for the PLL of 1 MHz (shame on me!). So, I changed DIV
to 20 and MUL to 109 to try to get a 55 MHz MCK with my 20 MHz
crystal.&lt;/p&gt;

&lt;p&gt;
MCK = 20M * (109+1) / (20*2) = 55 Mhz&lt;/p&gt;

&lt;p&gt;
Do you see a problem with that math? These settings don&amp;#39;t work
either. I had to reduce MUL till MCK was 28.5 MHz or less before I
could get my toggling I/O pin program to start up and run
reliably.&lt;/p&gt;

&lt;p&gt;
Still confuzed...&lt;br /&gt;
Dave.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: AT91SAM7S256 not coming out of RESET...</title><link>https://community.arm.com/thread/74337?ContentTypeID=1</link><pubDate>Wed, 06 Sep 2006 11:53:34 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7a461cd8-556e-48a7-98da-1fe50cf09996</guid><dc:creator>Roger Lynx</dc:creator><description>&lt;p&gt;&lt;p&gt;
&lt;i&gt;I&amp;#39;m using a 20 MHz crystal, with 1 flash read wait state, with
&lt;b&gt;MUL = 1401&lt;/b&gt; and &lt;b&gt;DIV = 255&lt;/b&gt;.&lt;/i&gt;&lt;/p&gt;

&lt;p&gt;
BTW, there is a limit of 180 MHz for the f_PLL output. Also, for
the flash the MCK must be outside 3-19 MHz range. I&amp;#39;d re-check the
math behind this problem.&lt;/p&gt;

&lt;p&gt;
See erratum:&lt;br /&gt;
40.1.2.1 MCK: Limited Master Clock Frequency Ranges&lt;br /&gt;
in 6175E&amp;ndash;ATARM&amp;ndash;04-Apr-06&lt;/p&gt;

&lt;p&gt;
I did run this MCU overclocked to about 70 MHz (core clock) before
it quit. You must be driving it harder yet, IMHO.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: AT91SAM7S256 not coming out of RESET...</title><link>https://community.arm.com/thread/46731?ContentTypeID=1</link><pubDate>Wed, 06 Sep 2006 10:02:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:97bd5728-948a-4d62-82bc-899f28661f48</guid><dc:creator>Dave Sudolcan</dc:creator><description>&lt;p&gt;&lt;p&gt;
Update...&lt;/p&gt;

&lt;p&gt;
I slowed MCK down to ~ 25 MHz (from ~ 55 MHz), and the symptom
appears to have gone away. I&amp;#39;ve checked and double checked all the
relevant datasheet sections, including the errata, and I don&amp;#39;t see
any reason I can&amp;#39;t have an MCK of ~ 55 Mhz. I&amp;#39;m using REV A parts
(AT91SAM7S256 AU A) parts.&lt;/p&gt;

&lt;p&gt;
I&amp;#39;m using a 20 MHz crystal, with 1 flash read wait state, with MUL
= 1401 and DIV = 255. This should create an MCK of ~ 54.95 MHz, which
should be okay as best as I can tell. If I slow MUL down to 637 the
symptom goes away. Can anyone tell me if the settings I&amp;#39;m trying to
use are valid or not, or if there&amp;#39;s anything else I should be
checking?&lt;/p&gt;

&lt;p&gt;
Again... I know this is probably considered slightly off topic,
since it&amp;#39;s not about the KEIL tools per se, but I am using KEIL tools
on this project ;-)&lt;/p&gt;

&lt;p&gt;
Dave.&lt;/p&gt;
&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>