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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>I2C Page Write problem</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/19255/i2c-page-write-problem</link><description> If a problem with the I2C-Bus. 
I use a 80C515C and a Philips PCF8582C2T EEPROM. 
I can write one or two bytes without problems. But when I write more than two bytes (for excample eight bytes) I can do it only one time. When I call the function again</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: I2C Page Write problem</title><link>https://community.arm.com/thread/46304?ContentTypeID=1</link><pubDate>Tue, 04 Jul 2006 03:04:57 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a5e75973-7ddc-4728-a247-f1bbb4848dba</guid><dc:creator>Axel Farr</dc:creator><description>&lt;p&gt;Did you check the timing? EEPROMs need a certain time to do the programming. In short, the programming performed after Reception of a page (in this case probable 8 Bytes), the device first has to clear the adressed region (duration of the erase is found in the data sheet) and then it must write the adressed region. This leads to a certain time gap, in which the device is occupied by internal operations. Some EEPROMs for the I2C-Bus have an Output labelled lile &amp;quot;BSY&amp;quot; which gets active during that time (it can be used to poll the end of the write process). Without additional connection simply by means of the I2C-Bus works the so-called &amp;quot;Ack polling&amp;quot;. This means, that during write process on the EEPOM memory your chip will not respond to any attempt to reach it on the bus. It seems not to be there, until the internal operation is finished. An &amp;quot;Ack polling&amp;quot; is done by doing a write cycle by the bus master, which writes 0 bytes. So it is just a write of the slave adress, followed by a stop condition. If the slave is present, it will pull the data line low after the adress is scanned, resulting in a valid acknowledge bit. If it is not present or is a EEPROM working internally, the ACK bit will not be low, the access is then terminated.&lt;br /&gt;
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Greetings, Axel&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>