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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>A problem about keil&amp;#39;s simulation of AT91SAM7S64</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/18943/a-problem-about-keil-s-simulation-of-at91sam7s64</link><description> When I use the keil to simulate the PDC of AT91SAM7S64 the problem come. I eable &amp;#39;ENDRX interrupt&amp;#39; and &amp;#39;RXBUFF interrupt&amp;#39; then trigger receiving data. When the RCR count to zero, then automaticly the RNPR loads to the RPR and the RNCR loads to the RCR</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: A problem about keil's simulation of AT91SAM7S64</title><link>https://community.arm.com/thread/87402?ContentTypeID=1</link><pubDate>Fri, 30 Sep 2005 00:28:16 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a05dc3b2-2749-45a1-a3ac-454d667a1353</guid><dc:creator>Keil Software Support Intl.</dc:creator><description>&lt;p&gt;The problem has been already fixed in CARM V2.40.  Please use the current version of the tools (&lt;a href="http://www.keil.com/demo/"&gt;http://www.keil.com/demo/&lt;/a&gt;).&lt;br /&gt;
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Reinhard&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: A problem about keil's simulation of AT91SAM7S64</title><link>https://community.arm.com/thread/44771?ContentTypeID=1</link><pubDate>Thu, 29 Sep 2005 00:30:07 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6492a4e7-7ca6-4b5e-825b-a82756eb9efb</guid><dc:creator>Lin godday</dc:creator><description>&lt;p&gt;Just now I Debug the program with the hareware of 7S64, I used the USART0 channel of the PDC. My idea is right, When the RCR count to zero, then automaticly the RNPR loads to the RPR and the RNCR loads to the RCR, and at the same time the &amp;#39;ENDRX interrupt&amp;#39; be triggered. But by the simulation of the software the &amp;#39;ENDRX interrupt&amp;#39; will not be triggered until the RCR count to zero again. So I think maybe this a bug of the simulation of 7S64. My idea is right?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>