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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>16 bit up down counter</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/18669/16-bit-up-down-counter</link><description> Hi 
 
I have to use a 16 bit up/down counter...... I wrote the code for that in at89c51. The counting is made in external interrupt 0. The pulses are given by a linear scale. 
the count values are stored in mem location 50 and 51. The up counting or</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: 16 bit up down counter</title><link>https://community.arm.com/thread/111882?ContentTypeID=1</link><pubDate>Wed, 04 Jan 2006 22:37:02 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:68a415f4-0c2d-4985-b2ed-b7a97156f94b</guid><dc:creator>kannan k</dc:creator><description>&lt;p&gt;Hi Erik&lt;br /&gt;
&lt;br /&gt;
The reason i said for going into extra hardware was that our resources are limited to the atmel family and we could go only up to the at89s8252.&lt;br /&gt;
As i have already posted before, the 8252 does have up/down counting (DCEN) but during down counting the timer values reset to zero.&lt;br /&gt;
&lt;br /&gt;
please correct me if i am wrong.&lt;br /&gt;
&lt;br /&gt;
kannan.k&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 16 bit up down counter</title><link>https://community.arm.com/thread/97754?ContentTypeID=1</link><pubDate>Wed, 04 Jan 2006 11:58:28 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:08e6ffa6-a26b-460b-b32c-f4642cd1914d</guid><dc:creator>erik  malund</dc:creator><description>&lt;p&gt;why extra hardware? there are derivatives (e.g. some SILabs) that have a bit specifying whether a timer count up or down&lt;br /&gt;
&lt;br /&gt;
from the Philips p89x51Rx2 datasheet:&lt;br /&gt;
&amp;quot;DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.&amp;quot;&lt;br /&gt;
&lt;br /&gt;
Erik&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 16 bit up down counter</title><link>https://community.arm.com/thread/73754?ContentTypeID=1</link><pubDate>Wed, 04 Jan 2006 09:26:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7533c00b-b411-4131-aa1e-3866b2c569ce</guid><dc:creator>kannan k</dc:creator><description>&lt;p&gt;Hi&lt;br /&gt;
&lt;br /&gt;
Thanks for the program Davis. I will try it out. But most proabaly we will have to use the extra hardware.&lt;br /&gt;
&lt;br /&gt;
Thaks once again for the help&lt;br /&gt;
&lt;br /&gt;
kannan.k&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 16 bit up down counter</title><link>https://community.arm.com/thread/45325?ContentTypeID=1</link><pubDate>Tue, 03 Jan 2006 12:38:17 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:9b70058c-d2d1-48c9-b60b-517b98030ea8</guid><dc:creator>Drew Davis</dc:creator><description>&lt;p&gt;How close are you to being able to handle the processing requirements?  We could make suggestions to improve the addition routine, but it probably won&amp;#39;t make a huge difference.  If you&amp;#39;re within a factor of two of being able to squeeze in the function, perhaps.  Otherwise, you&amp;#39;re going to need some hardware support or a faster CPU clock.&lt;br /&gt;
&lt;br /&gt;
Here&amp;#39;s one possible tweak to the code.  The 16-bit increment takes 6 instruction cycles, where the original took 12 (if both bytes needed to be incremented).  The main trick here is avoiding the push/pop of the accumulator thanks to the exchange (xch) instruction.&lt;br /&gt;
&lt;br /&gt;
You could replace the increment of the upper byte with a test of the carry and an inc.  This results in the same worst-case time, 3 cycles to increment the second byte, but only 2 cycles whenever the increment isn&amp;#39;t needed.  That is, 255/256ths of the time, it saves one clock.&lt;br /&gt;
&lt;br /&gt;
The 8051 assembly wizards in the forum might well be able to make more improvements.  (Maybe there&amp;#39;s a trick possible with INC DPTR, or DJNZ.)  But if your pulse rate is three or more times as high as you can currently handle, then there&amp;#39;s not much software optimization can do.&lt;br /&gt;
&lt;br /&gt;
&lt;pre&gt;
counter:
        jnb p3.0,ru
        jnb p3.1,rd
        reti

ru:     ; up counting
        xch  a,51h     ;1
        add  a,#01h    ;1
        xch  a,51h     ;1

        xch  a,50h     ;1
        addc a,#00h    ;1
        xch  a,50h     ;1

        reti           ;2

ru2:     ; up counting version 2
        xch  a,51h     ;1
        add  a,#01h    ;1
        xch  a,51h     ;1

        jnc UpDone     ;2
        inc 50h        ;1
UpDone:
        reti           ;2

&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>