<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>ST10F269 Features</title><link>https://community.arm.com/developer/tools-software/tools/f/keil-forum/17906/st10f269-features</link><description> Does anybody know if the ST10F269 Microcontroller supports the cached interrupt feature? - Thanks </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: ST10F269 Features</title><link>https://community.arm.com/thread/42684?ContentTypeID=1</link><pubDate>Sat, 28 Aug 2004 07:58:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:33916c78-b1b4-4692-a99e-6d6e0590773a</guid><dc:creator>Mik Kleshov</dc:creator><description>&lt;p&gt;You must be referring to one of the advanced features of the C166S V2 core, in which case the answer is no.&lt;br /&gt;
ST10F269 is a C166 V1-based microcontroller:&lt;br /&gt;
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- mike&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>